Processor Clock, PCK up to 200Mhz
- 220 MIPS at 200 MHz (1.1 Mips/Mhz)
Master Clock , MCK up to 100Mhz
80 Kbytes of FAST Internal SRAM
- Single access at MCK speed
- Supports ARM926 TCM interfaces
16 Kbytes of FAST Internal SRAM
- Single access at MCK speed
128 Kbytes of Internal ROM
- Dedicated Boot code: SAM Boot
- Single access at MCK speed
32-bit SDRAM Memory support
16-bit Static Memory, NAND Flash, Compact
BGA-324 package
16-KByte Data Cache, 16-KByte Instruction Cache
ARM V5TEJ architecture
ARM Jazelle : Java byte code acceleration achieved by hardware
DSP enhancement:
- Multiply instructions using a single-cycle 32*16 implementation
- Multiply or Multiply Accumulate (MAC) instructions
- Pipeline allows one multiply to start each cycle
Memory Management Unit (MMU)
Tightly-Coupled Memory (TCM):
- Separate interface for Instruction and Data
- Single access at Processor Speed
JTAG ICE support
Dual External Bus Interface (EBI0 and EBI1) frequency: up to 100Mhz
Mobile SDRAM support through the embedded SDRAM Controller
- Deep Power Down Mode support
- Partial array self-refresh and others Mobile SDRAM features
8-bit, 16-bit NAND Flash support through NAND Flash glue-logic
Compact Flash support through Compact Flash glue-logic (EBI1 only)
- Compact Flash access on SMC NCS4 and/or NCS5
- True IDE mode allows HDD devices access
2D Graphics Accelerator
- Line Draw, Block Transfer, Polygon fill, Clipping, Commands Queing
LCD Controller
- Supports Passive or Active Displays
- Up to 24-bit per pixel in TFT Mode, Up to 16-bit per pixel in STN color Mode
- Up to 16M Colors in TFT Mode, Resolution up to 2048x2048, supports wider screen buffers
- Virtual screen support
Image Sensor Interface
- ITU-R BT. 601/656 External Interface, programmable frame capture rate
- 12-bit data interface for support of highly sensitive sensors
- SAV and EAV synchronization, preview path with scaler, YCbCr format
One AC97 Controller (AC97C)
- 6-channels Single AC97 Analog Front end Interface, Slot Assigner
One Part 2.0A and Part 2.0B compliant CAN Controller
- 16 fully-programmable Message Object Mailboxes, 16-bit time stamp counter
One Four-channel 16-bit PWM Controller (PWMC)
2-ch DMA controller
- Single or Multi-block transfers
- Block chaining using linked list
- Auto-reloading
- Hardware handshaking
Engineering samples : Sept'06
Production : 1Q07
Summary Datasheet : July'06
Full Datasheet : July'06
Development board : Oct'06