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Which constraint should I use to suppress BlockRAM inference in Spartan 3E (VHDL)? I need to force the synthesizer to create a distributed RAM instead. Any help is appreciated.
read this doc: <ise_dir>/doc/usenglish/books/docs/cgd/cgd.pdf
Synthesis Constraints -> RAM_STYLE
Synthesis Constraints -> RAM_STYLE
Цитата(Constraints Guide @ Aug 19 2010, 00:00) 
RAM_STYLE is a synthesis constraint. It controls the way the macrogenerator implements the inferred RAM macros. Allowed values are AUTO, BLOCK and DISTRIBUTED. The default value is AUTO, meaning that XST looks for the best implementation for each inferred RAM. The implementation style can be manually forced to use block RAM or distributed RAM resources available in the Virtex and Spartan-II series.
Цитата
RAM_STYLE Syntax Examples
Before using RAM_STYLE, declare it with the following syntax:
After RAM_STYLE has been declared, specify the VHDL constraint as follows:
The default value is AUTO.
For a detailed discussion of the basic VHDL syntax, see ”Constraint Entry.”
Before using RAM_STYLE, declare it with the following syntax:
Код
attribute ram_style: string;
After RAM_STYLE has been declared, specify the VHDL constraint as follows:
Код
attribute ram_style of {signal_name|entity_name}: {signal|entity} is ”{auto|block|distributed}”;
The default value is AUTO.
For a detailed discussion of the basic VHDL syntax, see ”Constraint Entry.”
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