unsigned int volatile *pSDRAM;
  unsigned int  wCount;
  unsigned int  wRead,
                wWrite;
  
  printf ("CPU %d MHz\n",GetCPUFrequencyMhz() );
  printf ("PCK %d MHz\n",GetPCKFrequencyMhz() );

  while (1){
    printf("-T WR- 0x00000000\n");
   pSDRAM = (unsigned int *) BASE_EBI_CS1_ADDRESS;
   for ( wCount = 0,wWrite=0x0;wCount < 0x800000;wCount ++  ){
     *pSDRAM = wWrite;
     wRead = *pSDRAM;
     if (wWrite != wRead )
       printf ("[0x%08X] = 0x%08X ( 0x%08X,0x%08X)\n",wCount,wRead^wWrite,wRead,wWrite );
     pSDRAM++;
   }
}

//---- Инициализация PLLA = 200 MHz , PLLB = 48 MHz , PCK = 100MHz
init_PLL()
{
__var     tmp,
        var;

__message("Init Clock");
__writeMemory32(0x0000FF01,0xFFFFFC20,"Memory"); // PMC_MOR: MOSCEN = 1, enable main clock
while( (( var =__readMemory32(0xFFFFFC24,"Memory")) & (0x1 << 16))  == 0 ) { };  // wait time out

// AT91C_BASE_CKGR->CKGR_PLLAR = PLLAR_Register;
__writeMemory32(0x2030BF04,0xFFFFFC28,"Memory");
tmp = 0;
while( !(( var=__readMemory32(0xFFFFFC68,"Memory")) & ( 0x1 <<  1)) && (tmp++ < 100) ) {};

var = __readMemory32(0xFFFFFC28,"Memory");
__message "PLLAR=",var;

//AT91C_BASE_CKGR->CKGR_PLLBR = PLLBR_Register;
  __writeMemory32(0x10533F0E,0xFFFFFC2C,"Memory");
  tmp = 0;
  while( !((var = __readMemory32(0xFFFFFC68,"Memory")) & ( 0x1 <<  2)) && (tmp++ < 100) ) {};


  __writeMemory32( 0x1 ,0xFFFFFC30,"Memory");

  tmp = 0;
  while( !((var = __readMemory32(0xFFFFFC68,"Memory")) & (0x1 << 3)) && (tmp++ < 100) ) {};


//  AT91C_BASE_PMC->PMC_MCKR = MCKR_Register;
  __writeMemory32(0x00000102,0xFFFFFC30,"Memory");

  tmp = 0;
  while( !((var = __readMemory32(0xFFFFFC68,"Memory")) & (0x1 << 3)) && (tmp++ < 100) ) {};


}

//----------- Инициализация SDRAM 2х8х16 (2х MT48LC8M16A2-75)
init_SDRAM ()
{
__var i;
__message("Init SDRAM");

  __writeMemory32(0xFFFF0000,0xFFFFF800 +0x0070,"Memory");
  __writeMemory32(0x0,0xFFFFF800 +0x0074,"Memory");
  __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");      
  i = __readMemory32(0xFFFFFF60,"Memory");
  __writeMemory32(i|(0x1 << 1),0xFFFFFF60,"Memory");
  __writeMemory32( 0x0 ,0xFFFFFF64,"Memory");


__writeMemory32( 0x2A99C255,0xFFFFFF98,"Memory");

__writeMemory32(0x02,0xFFFFFF90,"Memory");
__writeMemory32(0x0,0x20000000,"Memory");
__writeMemory32(0x04,0xFFFFFF90,"Memory");

for(i=0;i<8;i++)
  __writeMemory32(0x0,0x20000000,"Memory");
__writeMemory32(0x3,0xFFFFFF90,"Memory");
__writeMemory32(0x0,0x20000000,"Memory");

__writeMemory32(0x610,0xFFFFFF94,"Memory");
__writeMemory32(0x00,0x20000000,"Memory");
__writeMemory32(0x0,0xFFFFFF90,"Memory");
__writeMemory32(0x0,0x20000000,"Memory");
}


execUserPreload()
{

init_PLL();
__writeMemory32(0xAAAAAAAA,0x00000000,"Memory");
  if(__readMemory32(0x00000000,"Memory") != 0xAAAAAAAA)
  {
    __writeMemory32(0x01,0xFFFFFF00,"Memory");    // MC_RCR: toggle remap bit
  }
init_SDRAM ();
  __message("Target init macro complete");
}

        MODULE    ?RESET
;        COMMON    INTVEC:CODE:NOROOT(2); Я убрал, линкер подразумевает эту секцию с 0 , но её мы будем копировать в SRAM
            RSEG    ICODE:CODE:NOROOT(2)
                PUBLIC  __program_start
        EXTERN    ?cstartup
;        EXTERN    undef_handler, swi_handler, prefetch_handler
;        EXTERN    data_handler, irq_handler, fiq_handler
        CODE32; Always ARM mode after reset    
ADRSTART:
        org    0x00+ADRSTART
__program_start
        ldr    pc,=?cstartup; Absolute jump
        org    0x04+ADRSTART
undef_handler:
        ldr    pc,=undef_handler
        org    0x08+ADRSTART
swi_handler:
        ldr    pc,=swi_handler
        org    0x0c+ADRSTART
prefetch_handler:
        ldr    pc,=prefetch_handler
        org    0x10+ADRSTART
data_handler:
        ldr    pc,=data_handler
        org    0x18+ADRSTART
    ldr pc, [pc,#-0xF20]  ; IRQ : read the AIC
        org    0x1c+ADRSTART
fiq_handler:
        ldr    pc,=fiq_handler

; Constant table entries (for ldr pc) will be placed at 0x20
        org    0x20+ADRSTART
        LTORG
;        ENDMOD    __program_start
                ENDMOD


;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
        MODULE    ?CSTARTUP

        RSEG    IRQ_STACK:DATA(2)
        RSEG    SVC_STACK:DATA:NOROOT(2)
        RSEG    CSTACK:DATA(2)
        RSEG    ICODE:CODE:NOROOT(2)
        PUBLIC    ?cstartup
        EXTERN    ?main

; Execution starts here.
; After a reset, the mode is ARM, Supervisor, interrupts disabled.


        CODE32
?cstartup

; Add initialization nedded before setup of stackpointers here


; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
                mrs     r0,cpsr                        ; Original PSR value
                bic     r0,r0,#MODE_BITS                  ; Clear the mode bits

.... дальше как было

  unsigned int volatile *pSDRAM, *pSDRAM1, *pSDRAM2;
  unsigned int  wCount;
  unsigned int  wRead,
                wWrite,
                wError,
                j,jmax;
  unsigned char bACount,
                nc,nr,nb,i;

  printf ("Main = %d Hz\n",AT91F_CKGR_GetMainClock(AT91C_BASE_CKGR, SLOWCLOCK));
  printf ("CPU = %d Hz\n",AT91F_PMC_GetProcessorClock(AT91C_BASE_PMC, AT91C_BASE_CKGR, SLOWCLOCK));

  printf ("\nSmart :) memory test (only 32 bit)\n");

  #define test_packet_size (8*1024)

  nc = 8 + (AT91C_BASE_SDRC->SDRC_CR & 0x03);          // columns
  nr = 11 + ((AT91C_BASE_SDRC->SDRC_CR >> 2) & 0x03); // rows
  nb = 1 + ((AT91C_BASE_SDRC->SDRC_CR >> 4) & 0x01);  // bancs
  bACount = nc + nr + nb;

  if (AT91C_BASE_SDRC->SDRC_MR & AT91C_SDRC_DBW_16_BITS)
    {
    printf ("Detected %d Mb of 16 bit SDRAM (not supported)\n", 1 << (bACount - 19)); // 16 bit
    while (1) {}
    }
  else
    printf ("Detected %d Mb of 32 bit SDRAM\n", 1 << (bACount - 18)); // 32 bit

//**********ADRESS LINES TEST
  printf("\nAdres lines test...\n");
  for (i = nc; i < bACount; i++)
    {
    if ( (1 << i) > test_packet_size)
      jmax = test_packet_size;
     else
      jmax = (1 << i);
    wError=0;
    srand (1);
    pSDRAM1 = (unsigned int *) BASE_EBI_CS1_ADDRESS;
    pSDRAM2 = (unsigned int *) BASE_EBI_CS1_ADDRESS + (1 << i);
    for (j = 0; j < jmax; j++)
      {
      *pSDRAM1 = rand(); pSDRAM1++;
      *pSDRAM2 = rand(); pSDRAM2++;
      }
    pSDRAM1 = (unsigned int *) BASE_EBI_CS1_ADDRESS;
    pSDRAM2 = (unsigned int *) BASE_EBI_CS1_ADDRESS + (1 << i);
    for (j = 0; j < jmax; j++)
      {
      if (*pSDRAM1 == *pSDRAM2)
        {
        wError++;
        }
      pSDRAM1++;
      pSDRAM2++;
      }
    if (i < nr + nc)
      printf ("A%d ",i-nc);
    else
      printf ("BA%d ",i-nc-nr);
    if (wError == 0)
      printf ("ok\n");
    else
      printf ("unconnected\n");
    }

//***********DATA LINE TEST*****
//***********SHORT**************
  printf("\nData line shorts test...\n");
  for (i = 0; i <= 31; i++)
    {
    wError = 0;
    wWrite = ~(1 << i);
    pSDRAM = (unsigned int *) BASE_EBI_CS1_ADDRESS;
    for (j = 0; j < test_packet_size; j++)
      {
      *pSDRAM = wWrite;
      pSDRAM++;
      }
    pSDRAM = (unsigned int *) BASE_EBI_CS1_ADDRESS;
    for (j = 0; j < test_packet_size; j++)
      {
      wRead = *pSDRAM;
      pSDRAM++;
      wError |= wWrite ^ wRead;
      }
    printf("D%d ",i);
    if (wError == 0)
      printf ("Ok\n");
    else
      {
      printf("shorts with ");
      for (j = 0; j <= 31; j++)
        if (wError & (1 << j))
          printf ("%d ",j);
      printf("\n");
      }
    }
//***********UNCONECT***********
  printf("\nData line uncon test...\n");

  wError = 0;
  pSDRAM = (unsigned int *) BASE_EBI_CS1_ADDRESS;
  for (j = 0; j < test_packet_size; j++)
    {
    *pSDRAM = 0;
    pSDRAM++;
    }
  pSDRAM = (unsigned int *) BASE_EBI_CS1_ADDRESS;
  for (j = 0; j < test_packet_size; j++)
    {
    wRead = *pSDRAM;
    pSDRAM++;
    wError |= wRead;
    }
  for (i = 0; i <= 31; i++)
    {
    printf("D%d ",i);
    if (wError & (1 << i))
      printf("unconect\n");
    else
      printf ("Ok\n");
    }

//***********RAND TEST********
  printf("\nRandom test...\n");
  while (1)
  {
   printf("\n-T WR- 0x00000000\n");
   srand(1);
   printf("First rand = 0x%8X\nStart filling\n",rand());
   pSDRAM = (unsigned int *) BASE_EBI_CS1_ADDRESS;
   for ( wCount = 0;wCount < (1 << (bACount -2)); wCount ++)
    {
    wWrite = rand ();
    *pSDRAM = wWrite;
    pSDRAM++;
    }
   wError = 0;
   srand(1);
   printf("First rand = 0x%8X\nStart testing\n",rand());
   pSDRAM = (unsigned int *) BASE_EBI_CS1_ADDRESS;
   for ( wCount = 0;wCount < (1 << (bACount -2)); wCount ++)
    {
    wRead = *pSDRAM;
    wWrite = rand();
    if (wRead != wWrite )
      {
      printf ("[0x%08X] = 0x%08X ( 0x%08X,0x%08X)\n",wCount,wRead^wWrite,wRead,wWrite );
      wError++;
      }
    pSDRAM++;
    }
   printf("Done. %d errors.\n",wError);
  }

4.18.2 Pseudo-random binary sequence generator
It is often necessary to generate (pseudo-) random numbers and the most efficient
algorithms are based on shift generators with exclusive-OR feedback rather like a
cyclic redundancy check generator. Unfortunately the sequence of a 32 bit generator
needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before
repetition), so this example uses a 33 bit register with taps at bits 33 and 20. The basic
algorithm is newbit:=bit 33 eor bit 20, shift left the 33 bit number and put in newbit at
the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). The
entire operation can be done in 5 S cycles:
; Enter with seed in Ra (32 bits),
Rb (1 bit in Rb lsb), uses Rc.
;
TST Rb,Rb,LSR#1; Top bit into carry
MOVS Rc,Ra,RRX; 33 bit rotate right
ADC Rb,Rb,Rb; carry into lsb of Rb
EOR Rc,Rc,Ra,LSL#12; (involved!)
EOR Ra,Rc,Rc,LSR#20; (similarly involved!)
; new seed in Ra, Rb as before

extern randtest(u_int *start_addr, u_int word_count, u_int *seed);

void ramtest(u_int address, u_int word_count)
{
    static u_int addr;
    static u_int seed[0x02] = {0xdeadbeef, 0xcafedeca};
    u_int pass = 0x00, fcount = 0x00;

    addr = address;
    while(0x01)
    {
        printf("%d:%d Testing RAM...", pass, fcount);
        if(randtest(&addr, word_count, seed) == 0x00)
        {
            pass++;
            printf ("Passed.\n\r");
        }
        else
        {
            fcount++;
            printf("Failed at 0x%08x, Exp: 0x%08x; Rcv: 0x%08x\n\r", addr, seed[0x00], *(volatile u_int *)addr);
            addr = address;
        }
    }
}

        EXPORT    randtest

        AREA    code0, CODE, READONLY

randtest
        stmfd    sp!, {r4-r6, lr}
        ldmia    r2, {r4, r5}
        ldr        r6, [r0]
        mov        r7, r1
0
        tst        r5, r5, lsr #0x01    ; to bit into carry
        movs    r12, r4, rrx        ; 33-bit rotate right
        adc        r5, r5, r5            ; carry into LSB of a2
        eor        r12, r12, r4, lsl #0x0c; (involved!)
        eor        r4, r12, r12, lsr #0x14; (similarly involved!)

        str        r4, [r6], #0x04
        subs    r7, r7, #0x01
        bne        %B0

        ldmia    r2, {r4, r5}
        ldr        r6, [r0]
1
        tst        r5, r5, lsr #0x01    ; to bit into carry
        movs    r12, r4, rrx        ; 33-bit rotate right
        adc        r5, r5, r5            ; carry into LSB of a2
        eor        r12, r12, r4, lsl #0x0c; (involved!)
        eor        r4, r12, r12, lsr #0x14; (similarly involved!)

        ldr        r12, [r6], #0x04
        cmp        r12, r4
        bne        %F2
        subs    r1, r1, #0x01
        bne        %B1
        stmia    r2, {r4, r5}
        mov        r0, #0x00
        ldmfd    sp!, {r4-r6, pc}
2
        sub        r6, r6, #0x04
        str        r6, [r0]
        stmia    r2, {r4, r5}
        mov        r0, #0x01
        ldmfd    sp!, {r4-r6, pc}

        END