При моделировании ядра на выходах всегда UUUUUUUUUUUUUUU. В даташитах ксайлинсовских диаграмки есть, а вот testbench они привести не захотели!
Само ядро я добавлял в свой проект как в книге у Зотова и проект этот уже полностью реализован, вот тока при моделировании мне приходилось все сигналы от ядра ручками задавать, а это не есть хорошо.
Полная версия этой страницы: Не могу промоделировать ядро PicoBlaze!
Форум разработчиков электроники ELECTRONIX.ru > Программируемая логика ПЛИС (FPGA,CPLD, PLD) > Системы на ПЛИС - System on a Programmable Chip (SoPC)
Для полноты картины не хватает исходников. Я, например, не телепат. 
Цитата(lexus.mephi @ Jan 20 2007, 02:33) 
При моделировании ядра на выходах всегда UUUUUUUUUUUUUUU.
Нормально моделируется (Modelsim 6.1f)...
Смотрите входные (для Picoblaze) сигналы, в том числе и те, что вы не используете.
Проверьте соединение с ROM.
Итак, у меня есть 2 исходных файла! Один - верхнего уровня иерархии и два нижнего уровня иерархии ( смотрите первый прикрепленный файл).
Для начала я хотел просто промоделировать память программ. По идее при изменении адреса там должны изменяться инструкции на выходе. Вот TB для этого:
=====================================================================
ARCHITECTURE behavior OF tb_porg_rom_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT prog_rom
PORT(
address : IN std_logic_vector(9 downto 0);
clk : IN std_logic;
instruction : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL address : std_logic_vector(9 downto 0) := (others=>'0');
--Outputs
SIGNAL instruction : std_logic_vector(17 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: prog_rom PORT MAP(
address => address,
instruction => instruction,
clk => clk
);
pClock: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
pProcess: process
begin
address <= "0000001101";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000001111";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000010001";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000111100";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000010101";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait; -- will wait forever
END PROCESS;
END;
=====================================================================
Результат моделирования во втором прикрепленном файле.
Потом я попробовал промоделировать все 3 компонента в целом:
=====================================================================
ARCHITECTURE behavior OF tb_kcpsm3_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT embedded_kcpsm3
PORT(
in_port : IN std_logic_vector(7 downto 0);
interrupt : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
read_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
interrupt_ack : OUT std_logic
);
END COMPONENT;
COMPONENT kcpsm3
PORT(
instruction : IN std_logic_vector(17 downto 0);
in_port : IN std_logic_vector(7 downto 0);
interrupt : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
address : OUT std_logic_vector(9 downto 0);
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
read_strobe : OUT std_logic;
interrupt_ack : OUT std_logic
);
END COMPONENT;
COMPONENT prog_rom
PORT(
address : IN std_logic_vector(9 downto 0);
clk : IN std_logic;
instruction : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL interrupt : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL in_port : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL port_id : std_logic_vector(7 downto 0);
SIGNAL write_strobe : std_logic;
SIGNAL read_strobe : std_logic;
SIGNAL out_port : std_logic_vector(7 downto 0);
SIGNAL interrupt_ack : std_logic;
SIGNAL address : std_logic_vector(9 downto 0) := (others=>'0');
SIGNAL instruction : std_logic_vector(17 downto 0) := (others=>'0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
full: embedded_kcpsm3 PORT MAP(
port_id => port_id,
write_strobe => write_strobe,
read_strobe => read_strobe,
out_port => out_port,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk
);
proc: kcpsm3 PORT MAP(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk
);
progrom: prog_rom PORT MAP(
address => address,
instruction => instruction,
clk => clk
);
pClock: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
pProcess: process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait; -- will wait forever
END PROCESS;
END;
====================================================================
Что из этого получилось я хотел прикрепить в третий прикрепленный файл, но он не поместился. Да вобщем-то там и смотреть то нечего - на выходах UUUUUUUUUUUUUUUUU
Для начала я хотел просто промоделировать память программ. По идее при изменении адреса там должны изменяться инструкции на выходе. Вот TB для этого:
=====================================================================
ARCHITECTURE behavior OF tb_porg_rom_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT prog_rom
PORT(
address : IN std_logic_vector(9 downto 0);
clk : IN std_logic;
instruction : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL address : std_logic_vector(9 downto 0) := (others=>'0');
--Outputs
SIGNAL instruction : std_logic_vector(17 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: prog_rom PORT MAP(
address => address,
instruction => instruction,
clk => clk
);
pClock: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
pProcess: process
begin
address <= "0000001101";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000001111";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000010001";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000111100";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000010101";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait; -- will wait forever
END PROCESS;
END;
=====================================================================
Результат моделирования во втором прикрепленном файле.
Потом я попробовал промоделировать все 3 компонента в целом:
=====================================================================
ARCHITECTURE behavior OF tb_kcpsm3_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT embedded_kcpsm3
PORT(
in_port : IN std_logic_vector(7 downto 0);
interrupt : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
read_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
interrupt_ack : OUT std_logic
);
END COMPONENT;
COMPONENT kcpsm3
PORT(
instruction : IN std_logic_vector(17 downto 0);
in_port : IN std_logic_vector(7 downto 0);
interrupt : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
address : OUT std_logic_vector(9 downto 0);
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
read_strobe : OUT std_logic;
interrupt_ack : OUT std_logic
);
END COMPONENT;
COMPONENT prog_rom
PORT(
address : IN std_logic_vector(9 downto 0);
clk : IN std_logic;
instruction : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL interrupt : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL in_port : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL port_id : std_logic_vector(7 downto 0);
SIGNAL write_strobe : std_logic;
SIGNAL read_strobe : std_logic;
SIGNAL out_port : std_logic_vector(7 downto 0);
SIGNAL interrupt_ack : std_logic;
SIGNAL address : std_logic_vector(9 downto 0) := (others=>'0');
SIGNAL instruction : std_logic_vector(17 downto 0) := (others=>'0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
full: embedded_kcpsm3 PORT MAP(
port_id => port_id,
write_strobe => write_strobe,
read_strobe => read_strobe,
out_port => out_port,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk
);
proc: kcpsm3 PORT MAP(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk
);
progrom: prog_rom PORT MAP(
address => address,
instruction => instruction,
clk => clk
);
pClock: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
pProcess: process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait; -- will wait forever
END PROCESS;
END;
====================================================================
Что из этого получилось я хотел прикрепить в третий прикрепленный файл, но он не поместился. Да вобщем-то там и смотреть то нечего - на выходах UUUUUUUUUUUUUUUUU
Очень похоже на то, что данные в памяти не проинициализированы. Но это нужно проверить.
(Закладочка Memories->View Contents по правой кнопке).
(Закладочка Memories->View Contents по правой кнопке).
Цитата(makc @ Jan 20 2007, 14:08)
Очень похоже на то, что данные в памяти не проинициализированы. Но это нужно проверить.
(Закладочка Memories->View Contents по правой кнопке).
(Закладочка Memories->View Contents по правой кнопке).
Это в моделсиме закладочка? Че-то найти не могу. Забыл написать - я использую ModelSim SE 6.1
Цитата(lexus.mephi @ Jan 20 2007, 18:28)
Цитата(makc @ Jan 20 2007, 14:08)
Очень похоже на то, что данные в памяти не проинициализированы. Но это нужно проверить.
(Закладочка Memories->View Contents по правой кнопке).
Это в моделсиме закладочка? Че-то найти не могу. Забыл написать - я использую ModelSim SE 6.1
Эта закладочка в той же линии, где и закладочки Project, Library, Sim, Files ...
См. картинку в приложении.
Ну да, там по нулям. И как быть?
Цитата(lexus.mephi @ Jan 20 2007, 19:06)
Ну да, там по нулям. И как быть?
И должны быть нули?
Если должны, то нужно смотреть путь прохождения данных на предмет того, в каком именно месте возникают неопределенные значения. Для этого нужно выделить на временной диаграмме интересующий сигнал, нажать на временной диаграмме правую кнопку мыши и выбрать пункт Show Drivers. После этого в появившемся окне проследить путь прохождения сигнала до его задатчика.
PS: И все-таки еще раз повторяю, что неплохо было бы прикрепить исходники моделируемых модулей и скрипты для их моделирования. Без этого сложно что-то предположить, т.к. вариантов много, а возможен любой из них.
Я имел ввиду что на этой закладке вообще пусто. Вот исходник программной памяти, но по нему трудно че-то сказать. TB к нему я выше приводил.
==================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity prog_rom is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end prog_rom;
--
architecture low_level_definition of prog_rom is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "4F01AF011FC04C105F80CA040A0054064B014B08CA040A01C801C90209000801";
attribute INIT_01 of ram_1024_x_18 : label is "400A4F80CF080F014F40402400B100A4002E410B400A541B4F02AF021FC05424";
attribute INIT_02 of ram_1024_x_18 : label is "0500040040038801400209005402490308018901542C480700B100A4002E410B";
attribute INIT_03 of ram_1024_x_18 : label is "8609850084045841C310A31F131007020609050104085839C320131007000600";
attribute INIT_04 of ram_1024_x_18 : label is "8602850084015851C304A307131087088604850084025849C308A30F13108706";
attribute INIT_05 of ram_1024_x_18 : label is "1300870686058502585FC301A30113108702860185055858C302A30313108704";
attribute INIT_06 of ram_1024_x_18 : label is "86035871C320A33F130087048606586BC340A37F13008708860285015865C380";
attribute INIT_07 of ram_1024_x_18 : label is "5881C304A30713008708587CC308A30F1300870686015877C310A31F13008702";
attribute INIT_08 of ram_1024_x_18 : label is "C21050925892420912708701588BC301A301130087025886C302A30313008704";
attribute INIT_09 of ram_1024_x_18 : label is "C21050A258A242091250162040948501C210509A589A420912601720408C8601";
attribute INIT_0A of ram_1024_x_18 : label is "C2100200C420C2108201C720C2108201C620C2100201C520A0001520409C8401";
attribute INIT_0B of ram_1024_x_18 : label is "00000000000000000000000000000000A00054B44F004F0C54B14F014F0CA000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "D07417417417415D15D0574157415741574003400DCD1DFC083FC343402348A0";
attribute INITP_01 of ram_1024_x_18 : label is "000000000000000000000000000000000000B4D28A69A28D7D0D7D0D7D1D0741";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"4F01AF011FC04C105F80CA040A0054064B014B08CA040A01C801C90209000801",
INIT_01 => X"400A4F80CF080F014F40402400B100A4002E410B400A541B4F02AF021FC05424",
INIT_02 => X"0500040040038801400209005402490308018901542C480700B100A4002E410B",
INIT_03 => X"8609850084045841C310A31F131007020609050104085839C320131007000600",
INIT_04 => X"8602850084015851C304A307131087088604850084025849C308A30F13108706",
INIT_05 => X"1300870686058502585FC301A30113108702860185055858C302A30313108704",
INIT_06 => X"86035871C320A33F130087048606586BC340A37F13008708860285015865C380",
INIT_07 => X"5881C304A30713008708587CC308A30F1300870686015877C310A31F13008702",
INIT_08 => X"C21050925892420912708701588BC301A301130087025886C302A30313008704",
INIT_09 => X"C21050A258A242091250162040948501C210509A589A420912601720408C8601",
INIT_0A => X"C2100200C420C2108201C720C2108201C620C2100201C520A0001520409C8401",
INIT_0B => X"00000000000000000000000000000000A00054B44F004F0C54B14F014F0CA000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"D07417417417415D15D0574157415741574003400DCD1DFC083FC343402348A0",
INITP_01 => X"000000000000000000000000000000000000B4D28A69A28D7D0D7D0D7D1D0741",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
=====================================================================
==================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity prog_rom is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end prog_rom;
--
architecture low_level_definition of prog_rom is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "4F01AF011FC04C105F80CA040A0054064B014B08CA040A01C801C90209000801";
attribute INIT_01 of ram_1024_x_18 : label is "400A4F80CF080F014F40402400B100A4002E410B400A541B4F02AF021FC05424";
attribute INIT_02 of ram_1024_x_18 : label is "0500040040038801400209005402490308018901542C480700B100A4002E410B";
attribute INIT_03 of ram_1024_x_18 : label is "8609850084045841C310A31F131007020609050104085839C320131007000600";
attribute INIT_04 of ram_1024_x_18 : label is "8602850084015851C304A307131087088604850084025849C308A30F13108706";
attribute INIT_05 of ram_1024_x_18 : label is "1300870686058502585FC301A30113108702860185055858C302A30313108704";
attribute INIT_06 of ram_1024_x_18 : label is "86035871C320A33F130087048606586BC340A37F13008708860285015865C380";
attribute INIT_07 of ram_1024_x_18 : label is "5881C304A30713008708587CC308A30F1300870686015877C310A31F13008702";
attribute INIT_08 of ram_1024_x_18 : label is "C21050925892420912708701588BC301A301130087025886C302A30313008704";
attribute INIT_09 of ram_1024_x_18 : label is "C21050A258A242091250162040948501C210509A589A420912601720408C8601";
attribute INIT_0A of ram_1024_x_18 : label is "C2100200C420C2108201C720C2108201C620C2100201C520A0001520409C8401";
attribute INIT_0B of ram_1024_x_18 : label is "00000000000000000000000000000000A00054B44F004F0C54B14F014F0CA000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "D07417417417415D15D0574157415741574003400DCD1DFC083FC343402348A0";
attribute INITP_01 of ram_1024_x_18 : label is "000000000000000000000000000000000000B4D28A69A28D7D0D7D0D7D1D0741";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"4F01AF011FC04C105F80CA040A0054064B014B08CA040A01C801C90209000801",
INIT_01 => X"400A4F80CF080F014F40402400B100A4002E410B400A541B4F02AF021FC05424",
INIT_02 => X"0500040040038801400209005402490308018901542C480700B100A4002E410B",
INIT_03 => X"8609850084045841C310A31F131007020609050104085839C320131007000600",
INIT_04 => X"8602850084015851C304A307131087088604850084025849C308A30F13108706",
INIT_05 => X"1300870686058502585FC301A30113108702860185055858C302A30313108704",
INIT_06 => X"86035871C320A33F130087048606586BC340A37F13008708860285015865C380",
INIT_07 => X"5881C304A30713008708587CC308A30F1300870686015877C310A31F13008702",
INIT_08 => X"C21050925892420912708701588BC301A301130087025886C302A30313008704",
INIT_09 => X"C21050A258A242091250162040948501C210509A589A420912601720408C8601",
INIT_0A => X"C2100200C420C2108201C720C2108201C620C2100201C520A0001520409C8401",
INIT_0B => X"00000000000000000000000000000000A00054B44F004F0C54B14F014F0CA000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"D07417417417415D15D0574157415741574003400DCD1DFC083FC343402348A0",
INITP_01 => X"000000000000000000000000000000000000B4D28A69A28D7D0D7D0D7D1D0741",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
=====================================================================
На будущее - не нужно цитировать файлы. Их можно заархивировать и прикрепить к сообщению. Так будет намного удобнее всем и правильнее.
Теперь по поводу проблемы. По всей видимости есть ошибки в самом процессе моделирования. Поскольку у меня все нормально промоделировалось с использованием приведенных исходников и файла-проекта, созданного мною. Пример и подтверждение успешного моделирования находятся в приложении.
Теперь по поводу проблемы. По всей видимости есть ошибки в самом процессе моделирования. Поскольку у меня все нормально промоделировалось с использованием приведенных исходников и файла-проекта, созданного мною. Пример и подтверждение успешного моделирования находятся в приложении.
А у тебя какой ModelSim? Я просто заметил, что у тебя в uut есть вкладка ram, а у меня такой вкладки нету. Как ее подключить?
Во че пишет!
# ** Warning: (vsim-3473) Component instance "ram_1024_x_18 : ramb16_s18" is not bound.
# Time: 0 ps Iteration: 0 Region: /tb_porg_rom_vhd/uut File: PROG_ROM.VHD
Во че пишет!
# ** Warning: (vsim-3473) Component instance "ram_1024_x_18 : ramb16_s18" is not bound.
# Time: 0 ps Iteration: 0 Region: /tb_porg_rom_vhd/uut File: PROG_ROM.VHD
Цитата(lexus.mephi @ Jan 20 2007, 22:49)
А у тебя какой ModelSim? Я просто заметил, что у тебя в uut есть вкладка ram, а у меня такой вкладки нету. Как ее подключить?
У меня QuestaSim 6.2e. Но это роли не играет, т.к. эта вкладка есть и ModelSim'e и в QuestaSim'e.
Дело в другом:
Цитата
Во че пишет!
# ** Warning: (vsim-3473) Component instance "ram_1024_x_18 : ramb16_s18" is not bound.
# Time: 0 ps Iteration: 0 Region: /tb_porg_rom_vhd/uut File: PROG_ROM.VHD
# ** Warning: (vsim-3473) Component instance "ram_1024_x_18 : ramb16_s18" is not bound.
# Time: 0 ps Iteration: 0 Region: /tb_porg_rom_vhd/uut File: PROG_ROM.VHD
Это говорит лишь о том, что он не нашел скомпилированной версии требующейся библиотеки (unisim).
Без него нормальное моделирование невозможно (неоткуда браться данным). Все встало на свои места.
Для того, чтобы моделировать эти компоненты, нужно для начала откомпилировать системные библиотеки ISE через меню проекта (там есть пункт Compile Simulation Libraries).
Макс, спасибо тебе огромное!!! Я подумывал что это из-за библиотек, но unisim у меня вроде откомпилина. И к тому же до этого, если у меня были проблемы с библиотеками, то ModelSim вообще не запускался. )) Ща попробую перекомпилить.
УРА!!! Перекомпилил и все пучком =))) Еще раз огромное спасибо, Макс!!! P.S. Тему как-то можно закрыть? Или это дело админов?
Кнопка внизу из опций модератора, которые доступны автору темы.
Тема закрыта.
Тема закрыта.
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