...
SRAM_ADDR: out std_logic_vector (17 downto 0);
SRAM_DATA: inout std_logic_vector (15 downto 0);
SRAM_OE: out std_logic;
SRAM_WE: out std_logic;
SRAM_UB: out std_logic;
SRAM_LB: out std_logic;
SRAM_CE: out std_logic;
...
ADDR : in std_logic_vector (17 downto 0);
DATA_READ: out std_logic_vector (15 downto 0);
DATA_WRITE: in std_logic_vector (15 downto 0);
...

SRAM_ADDR <= ADDR;
SRAM_OE <= '1';
SRAM_WE <= '0';
SRAM_CE <= '0';
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_DATA <= DATA_WRITE;

--SRAM_ADDR <= ADDR; -- адрес не переключаю, на шине - KEEPER
SRAM_OE <= '0';
SRAM_WE <= '1';
SRAM_CE <= '0';
SRAM_LB <= '0';
SRAM_UB <= '0';
DATA_READ <= SRAM_DATA;

SRAM_DATA<="ZZ...ZZ";
DATA_READ <= SRAM_DATA;

  SRAMDataBus_i : for i in (C_DWIDTH-1) downto 0 generate
     SRAMDataBit_i : iobuf
       port map (
            I  => mem_Data_O(i),
          IO => mem_Data_pin(i),
          O  => mem_Data_I(i),
          T  => mem_Data_T(i)
         );
  end generate;

data = 'bZ;
read_data = data;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY vhdl_sram IS
    PORT
    (
        clk        : IN    STD_LOGIC;
        rst        : IN    STD_LOGIC;
        -- Сигналы для SRAM
        address    : OUT    STD_LOGIC_VECTOR(16 downto 0);
        data    : INOUT    STD_LOGIC_VECTOR(7 downto 0);
        oe_n    : OUT    STD_LOGIC;
        ce_n    : OUT    STD_LOGIC;
        we_n    : OUT    STD_LOGIC;
        -- Считанное назад значение
        readed_data    : OUT    STD_LOGIC_VECTOR(7 downto 0)
    );
END vhdl_sram;

ARCHITECTURE rtl OF vhdl_sram IS
    TYPE state_type IS (state1, state2, state3);
    SIGNAL state: state_type;
    
    --SIGNAL    cnt    : UNSIGNED(4 DOWNTO 0);
    SIGNAL    cnt    : INTEGER RANGE 0 TO 31;
BEGIN

    PROCESS (clk, rst)
    BEGIN
        IF rst='1' THEN
            cnt <= 0;
        ELSIF (clk'EVENT AND clk = '1') THEN
            cnt <= cnt + 1;
        END IF;
    END PROCESS;
    
    PROCESS (clk, rst)
    BEGIN
        IF (rst='1') THEN
                    address <= B"0_0000_0000_0000_0000";
                    data <= (others => 'Z');
                    ce_n <= '1';
                    oe_n <= '1';
                    we_n <= '1';
                    readed_data <= B"0000_0000";
        ELSIF (clk'EVENT AND clk = '1') THEN
            CASE cnt IS
                WHEN 0 =>
                    address <= B"0_0000_0000_0000_0000";
                    data <= B"0110_1010";
                    ce_n <= '1';
                    oe_n <= '1';
                    we_n <= '1';
                    
                WHEN 1 =>
                    ce_n <= '0';
                    we_n <= '0';
                    
                WHEN 2 =>
                    ce_n <= '1';
                    we_n <= '1';
                    
                WHEN 3 =>
                    address <= B"0_0000_0000_0000_0001";
                    data <= B"1100_0101";
                    
                WHEN 4 =>
                    ce_n <= '0';
                    we_n <= '0';

                WHEN 5 =>
                    ce_n <= '1';
                    we_n <= '1';
                    
                WHEN 6 =>
                    address <= B"0_0000_0000_0000_0000";
                    data <= (others => 'Z');
                
                WHEN 7 =>
                    ce_n <= '0';
                    oe_n <= '0';
                    
                WHEN 15 =>
                    readed_data <= data;
                    
                WHEN 16 =>
                    ce_n <= '1';
                    oe_n <= '1';
                    
                WHEN OTHERS => NULL;
                    
            END CASE;
        END IF;
    END PROCESS;
END rtl;