AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_ADC) | (1<<AT91C_ID_TC0);
    AT91C_BASE_TCB->TCB_TC0.TC_CCR = AT91C_TC_CLKDIS;                    // disable TC0 clock
    AT91C_BASE_TCB->TCB_TC1.TC_CCR = AT91C_TC_CLKDIS;                    // disable TC1 clock
    AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;

    AT91C_BASE_TCB->TCB_TC0.TC_IDR = AT91C_TC_ETRGS
                        | AT91C_TC_LDRBS | AT91C_TC_LDRAS \
                        | AT91C_TC_CPCS | AT91C_TC_CPBS | AT91C_TC_CPAS \
                        | AT91C_TC_LOVRS | AT91C_TC_COVFS;
    AT91C_BASE_TCB->TCB_TC0.TC_CMR =
                          AT91C_TC_BSWTRG_NONE | AT91C_TC_BEEVT_NONE | AT91C_TC_BCPC_SET | AT91C_TC_BCPB_CLEAR // TIOB: set on RB, clear on RC
                        | AT91C_TC_ASWTRG_NONE | AT91C_TC_AEEVT_NONE | AT91C_TC_ACPC_SET | AT91C_TC_ACPA_CLEAR // TIOA: set on RC, clear on RA
                        | AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO                        // waveform mode, up to RC
                        | AT91C_TC_ENETRG | AT91C_TC_EEVT_XC2 | AT91C_TC_EEVTEDG_NONE     // no ext. trigger
                        | (0 * AT91C_TC_CPCDIS) | (0 * AT91C_TC_CPCSTOP) | AT91C_TC_BURST_NONE | (0 * AT91C_TC_CLKI) | AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
#define    T0CLK    (MCK / 2)
    AT91C_BASE_TCB->TCB_TC0.TC_RA = 1;
    AT91C_BASE_TCB->TCB_TC0.TC_RB = T0CLK / ADC_SAMPLE_RATE / 2 - 1;
    AT91C_BASE_TCB->TCB_TC0.TC_RC = T0CLK / ADC_SAMPLE_RATE - 1;

    AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;

    AT91C_BASE_ADC->ADC_RPR = (uintptr_t)Buffer[1];
    AT91C_BASE_ADC->ADC_RCR = sizeof(Buffer[0]);
    AT91C_BASE_ADC->ADC_RNPR = (uintptr_t)Buffer[2];
    AT91C_BASE_ADC->ADC_RNCR = sizeof(Buffer[0]);

    AT91C_BASE_ADC->ADC_PTCR = AT91C_PDC_RXTEN;

    AT91C_BASE_ADC->ADC_MR =(4 * AT91C_ADC_SHTIM / 0x0F) | (0 * AT91C_ADC_STARTUP / 0x1F) | (2 * AT91C_ADC_PRESCAL / 0x3F)
                         | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_LOWRES_8_BIT | AT91C_ADC_TRGSEL_TIOA0 | AT91C_ADC_TRGEN_EN;
    AT91C_BASE_ADC->ADC_CHDR = (1<<7) | (0<<6) | (0<<5) | (1<<4) | (1<<3) | (1<<2) | (1<<1) | (1<<0);
    AT91C_BASE_ADC->ADC_CHER = (0<<7) | (1<<6) | (1<<5) | (0<<4) | (0<<3) | (0<<2) | (0<<1) | (0<<0);
    AT91C_BASE_ADC->ADC_IER = AT91C_ADC_ENDRX;

    AT91C_BASE_AIC->AIC_SMR[AT91C_ID_ADC] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST;
    AT91C_BASE_AIC->AIC_SVR[AT91C_ID_ADC] = (uint32_t)IRQ_Handler;
    AT91C_BASE_AIC->AIC_IECR = (1<<AT91C_ID_ADC);