raspisyvaü situaciü:
usb (Cy7C68013) dol*en generirovat' na primer 4isla i otkladyvat' k primeru na EP6. a ja na kompe s4ityvaju eti 4isla s EP6.
vtoroj den' mu4aüs' i ne mogu ponjat' gde tut oshibka, etc.
kak primer beru example 'bulkloop' von cypress i menjaü tam TD_Pool():
Код
void TD_Poll(void) // Called repeatedly while the device is idle
{
WORD i;
WORD count;
// if(!(EP2468STAT & bmEP2EMPTY))
// { // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
[b]if(!(EP2468STAT & bmEP6FULL))
{ // check EP6 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
for(i = 0; i < 64; i++)
{
EP6FIFOBUF[i] = i + 1;
}
EP6BCH = 0x00;
SYNCDELAY;
EP6BCL = 0x40;
}
else
{
//SYNCDELAY;
//EP6BCL = 0x80; // re(arm) EP6OUT
}[/b]
// }
if(!(EP2468STAT & bmEP4EMPTY))
{ // check EP4 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP8FULL))
{ // check EP8 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
APTR1H = MSB( &EP4FIFOBUF );
APTR1L = LSB( &EP4FIFOBUF );
AUTOPTRH2 = MSB( &EP8FIFOBUF );
AUTOPTRL2 = LSB( &EP8FIFOBUF );
count = (EP4BCH << 8) + EP4BCL;
// loop EP4OUT buffer data to EP8IN
for( i = 0x0000; i < count; i++ )
{
// setup to transfer EP4OUT buffer to EP8IN buffer using AUTOPOINTER(s)
EXTAUTODAT2 = EXTAUTODAT1;
}
EP8BCH = EP4BCH;
SYNCDELAY;
EP8BCL = EP4BCL; // arm EP8IN
SYNCDELAY;
EP4BCL = 0x80; // re(arm) EP4OUT
}
}
}
{
WORD i;
WORD count;
// if(!(EP2468STAT & bmEP2EMPTY))
// { // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
[b]if(!(EP2468STAT & bmEP6FULL))
{ // check EP6 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
for(i = 0; i < 64; i++)
{
EP6FIFOBUF[i] = i + 1;
}
EP6BCH = 0x00;
SYNCDELAY;
EP6BCL = 0x40;
}
else
{
//SYNCDELAY;
//EP6BCL = 0x80; // re(arm) EP6OUT
}[/b]
// }
if(!(EP2468STAT & bmEP4EMPTY))
{ // check EP4 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP8FULL))
{ // check EP8 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
APTR1H = MSB( &EP4FIFOBUF );
APTR1L = LSB( &EP4FIFOBUF );
AUTOPTRH2 = MSB( &EP8FIFOBUF );
AUTOPTRL2 = LSB( &EP8FIFOBUF );
count = (EP4BCH << 8) + EP4BCL;
// loop EP4OUT buffer data to EP8IN
for( i = 0x0000; i < count; i++ )
{
// setup to transfer EP4OUT buffer to EP8IN buffer using AUTOPOINTER(s)
EXTAUTODAT2 = EXTAUTODAT1;
}
EP8BCH = EP4BCH;
SYNCDELAY;
EP8BCL = EP4BCL; // arm EP8IN
SYNCDELAY;
EP4BCL = 0x80; // re(arm) EP4OUT
}
}
}
izmenenno v principe tol'ko odno mesto (*irnyj shirft)
moja proga 4itaet EP6. ona to4no rabotaet, tak kak proverjal na origenale (bulkloop).
nadeüs' raspisaml problemu doskonal'no.
pomogite naiti oshibku. ili esli u kogoto podobnaja proga est', to skin'te na borja@htwg-konstanz.de
blagodarü za ranee