void ADC_Init(void)
{
  PORTA &= ~(1<<RST);
  PORTA |= (1<<RST);
  while(PINA&(1<<DRDY)); //wait for /DRDY to go low
}

//
// AD7730L setting
#define STANDBY   PA2
#define RST           PA3
#define DRDY         PA4
#define DOUT         PA5
#define DIN           PA6
#define SCLK         PA7
//----------------------------------------------------------------------------------#############################################################################
// Initiating a Self-Calibration after Power-On/Reset AD7730L
//_____________________________________________________________________________
void ADC_Init(void)
{
  PORTA &= ~(1<<RST);
  PORTA |= (1<<RST)|(1<<DIN);

  //Отправить 32 "1"
  for(unsigned char i=0;i<32;i++)
  {
    PORTA &= ~(1<<SCLK);
    delay_ns(50);
    PORTA |= (1<<SCLK);
  }

  WriteToReg(0x03, 8); //Writes to Communications Register Setting: Next Operation as Write to Filter Register
  WriteToReg(0x800010, 24); //Writes to Filter Register Setting: a 50 Hz Output Rate in CHOP Mode
  WriteToReg(0x02, 8); //Writes to Communications Register Setting: Next Operation as Write to Mode Register
  WriteToReg(0xb190, 16); //Writes to Mode Register: Initiating Internal Full-Scale Calibration for -20 mV to +20 mV Input Range
  while(PINA&(1<<DRDY)); //wait for /DRDY to go low

  WriteToReg(0x02, 8); //Writes to Communications Register Setting: Next Operation as Write to Mode Register
  WriteToReg(0x9190, 16); //Writes to Mode Register: Initiating Internal Zero-Scale Calibration for -20 mV to +20 mV Input Range
  while(PINA&(1<<DRDY)); //wait for /DRDY to go low
}
///////////////////////////////////////////////////////////////
//______________________________________________________________________________
void WriteToReg(unsigned long data, unsigned char reglength)
{
  unsigned int count=0;

  DDRA |= (1<<DIN);       // DIN -> output

  do{
    PORTA |= (1<<SCLK);   // SCLK = 1

    if( data & (1<<reglength) )
      PORTA |= (1<<DIN);  // DIN = 1
    else
      PORTA &= ~(1<<DIN); // DIN = 0

    delay_ns(50);         // 50 ns Data Valid to SCLK Edge Setup Time
    PORTA &= ~(1<<SCLK);  // SCLK = 0
    data = data << 1;
    count++;
    }while(count < reglength);
}

//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
void main(void)
{
// Initialise
  DDRA  = (1<<STANDBY)|(1<<RST)|(1<<DIN)|(1<<SCLK); //DOUT, DRDY -> input
  PORTA = (1<<STANDBY)|(1<<RST)|(1<<DRDY)|(1<<DOUT)|(1<<DIN); //pullups ON
................
}