//-------------------------------------------------------
void Init_Emac(void)
{
  AT91F_EMAC_CfgPMC();
  AT91F_EMAC_CfgPIO();
}

//-------------------------------------------------------

void EMAC_MII_WRITE_PHY(unsigned int REGA, unsigned int DATA)
{
AT91C_BASE_EMAC->EMAC_MAN=((DATA<<0 & 0xFFF)|   // 0x00 - 0x15 - DATA segment
                            (0x2<<16)|           // 0x16 - 0x17 CODE segment
                            (REGA << 18 & 0x1F)| // 0x18 - 0x22 REGA segment
                            (0x0<<23)|           // 0x23 - 0x27 PHYA segment
                            (0x1<<28)|           // 0x28 - 0x29 READ-WRITE
                            (0x0<<30));          // 0x30 - 0x31 Start of frame
}

//-------------------------------------------------------

void Config_Emac (void)
{
  AT91C_BASE_EMAC->EMAC_USRIO=(AT91C_EMAC_CLKEN);
    //  ** Config Network Control Register
  AT91C_BASE_EMAC->EMAC_NCR=(0x0<<0)|(0x0<<4)|(0x0<<8)|(0x0<<12)|
                            (0x0<<16)|(0x0<<20)|(0x0<<24)|(0x0<<28);
  Delay(0x2);
  AT91C_BASE_EMAC->EMAC_NCR=(0x1<<0);
  Delay(0x2);
  AT91C_BASE_EMAC->EMAC_NCR|=(0xc<<0);
  
  Delay(0x2);  

  
//  ** Configure Network Configuration Register
  
  
    AT91C_BASE_EMAC->EMAC_NCFGR=(AT91C_EMAC_SPD) // Set to 100 MBP's
                               |(AT91C_EMAC_FD)  // Set to full duplex
                               |(AT91C_EMAC_CAF)// Set to copy all frames
                               |(AT91C_EMAC_CLK_HCLK_8) // clock ratio MCK/8
                               |(AT91C_EMAC_RBOF_OFFSET_0) // Zero ofset  from bufer start
                               |(AT91C_EMAC_DRFCS); // Discard frame chk summ
                                  
    Delay(0x2);
    AT91C_BASE_EMAC->EMAC_NCFGR=(AT91C_EMAC_SPD) // Set to 100 MBP's
                               |(AT91C_EMAC_FD)  // Set to full duplex
                               |(AT91C_EMAC_CAF);// Set to copy all frames
    Delay(0x2);  
    EMAC_MII_WRITE_PHY(0x00, 0x1<<12 );//REGA,DATA
    Delay(0x2);
    EMAC_MII_WRITE_PHY(DM_ANAR, DM_ANAR_TX_FDX );//REGA,DATA
}