Код
PXA27x has 4 scan chains, controlled from a single JTAG style TAP controller. These are referred to as scan chains 0, 1, 2, and 3 and are arranged as shown in Figure 26-2, “PXA27x Scan Chain Arrangement”. The scan chains are selected by a TAP controller instruction (какой???).
Scan Chain 0. This allows access to the PXA27x core. The scan chain’s functions allow inter-macrocell testing (EXTEST), and allow the core’s test patterns to be applied serially (INTEST). The order of the scan chain (from TDI to TDO) sequentially:
1. Data bus bits 0 through 3
2. Control signals (order to be determined)
3. Address bus bits 31 through 0
Scan Chain 1. This is a small scan chain which only allows access to the core’s data bus. There are 32 scan
cells in this chain. This scan chain is used during debug to insert instructions into the
processor’s pipeline and capture the internal state as it is written. The order of the scan chain
is (from TDI to TDO): data bus bits 0 through 31.
Scan Chain 2. This is a scan chain around the PXA27x ICEbreaker macrocell. This allows the watchpoint
registers to be programmed and tested.
Scan Chain 3. This is a scan chain around the whole of the PXA27x. The scan chain allows the PXA27x
core to be exercised (INTEST) and allows inter-device testing at a board level (EXTEST).
The order of the scan chain is to be determined.
Note: Scan Chains 0 and 1 are not fully JTAG compliant in that data cannot be moved around the chains
without affecting the scan cell outputs. Use these scan chains only in debug state when the core is
not being clocked.conform
The PXA27x processor supports the mandatory public boundary-scan instructions, optional public
instructions, user-defined instructions, and private instructions listed in Table 26-2. The processor
does not support the IEEE 1149.1 optional public instructions runbist, intest, and usercode.
Scan Chain 0. This allows access to the PXA27x core. The scan chain’s functions allow inter-macrocell testing (EXTEST), and allow the core’s test patterns to be applied serially (INTEST). The order of the scan chain (from TDI to TDO) sequentially:
1. Data bus bits 0 through 3
2. Control signals (order to be determined)
3. Address bus bits 31 through 0
Scan Chain 1. This is a small scan chain which only allows access to the core’s data bus. There are 32 scan
cells in this chain. This scan chain is used during debug to insert instructions into the
processor’s pipeline and capture the internal state as it is written. The order of the scan chain
is (from TDI to TDO): data bus bits 0 through 31.
Scan Chain 2. This is a scan chain around the PXA27x ICEbreaker macrocell. This allows the watchpoint
registers to be programmed and tested.
Scan Chain 3. This is a scan chain around the whole of the PXA27x. The scan chain allows the PXA27x
core to be exercised (INTEST) and allows inter-device testing at a board level (EXTEST).
The order of the scan chain is to be determined.
Note: Scan Chains 0 and 1 are not fully JTAG compliant in that data cannot be moved around the chains
without affecting the scan cell outputs. Use these scan chains only in debug state when the core is
not being clocked.conform
The PXA27x processor supports the mandatory public boundary-scan instructions, optional public
instructions, user-defined instructions, and private instructions listed in Table 26-2. The processor
does not support the IEEE 1149.1 optional public instructions runbist, intest, and usercode.
т.е. проблема в том, что отсутствует информация как выбрать scan chain (не указан даже код
инструкции SCAN_N не говоря о количестве бит для DR при выборе) и нет описания регистров для scan chain 1 и 2. Это типа закрытая инфа (private instructions и пр.) или я плохо искал? Спасибо-)