Пролистал OPB_EMC.pdf (ver 2.00a) десятки раз и так и ненашёл понятной времянки для параметров
Цитата
Read cycle Chip Enable low to Data Valid. (5,6) C_TCEDV_PS_MEM_x(1)
Read cycle Address Valid to Data Valid. (5,7) C_TAVDV_PS_MEM_x(1)
Read cycle Chip Enable high to Data Bus High Impedance. (8,9) C_THZCE_PS_MEM_x(1)
Read cycle Output Enable high to Data Bus High Impedance. (8,10) C_THZOE_PS_MEM_x(1)
Write cycle time (4,11) C_TWC_PS_MEM_x(1)
Write Enable minimum pulse width. (4,12) C_TWP_PS_MEM_x(1)
Write cycle Write Enable high to Data Bus Low Impedance. (13,14) C_TLZWE_PS_MEM_x(1)
Notes:
1.x = values for memory banks 0 to 3
2.This design can accommodate up to 4 banks of memory. The address range generics are designated as C_MEM0_BASEADDR, C_MEM1_BASEADDR, C_MEM0_HIGHADDR, C_MEM1_HIGHADDR, etc.
3.No default value will be specified for C_MEMx_BASEADDR, C_MEMx_HIGHADDR to insure that the actual value is set, i.e. if the value is not set, a compiler error will be generated. These generics must be a power of 2 and encompass the memory size for C_MEMx_BASEADDR, C_MEMx_HIGHADDR.
4.Write enable low time is the maximum of C_TWC_PS_MEM and C_TWP_PS_MEM.
5.Read cycle time is the maximum of C_TCEDV_PS_MEM and C_TAVDV_PS_MEM.
6.Chip Enable low to Data Valid, C_TCEDV_PS_MEM, is equivalent to tACE for asynchronous SRAM and tELQV for FLASH in the respective memory device data sheets.
7.Address Valid to Data Valid, C_TAVDV_PS_MEM, is equivalent to tAA for asynchronous SRAM and tAVQV for FLASH in the respective memory device data sheets.
8.Read cycle recovery to write is the maximum of C_THZCE_PS_MEM and C_THZOE_PS_MEM.
9.Chip Enable high to data bus High Impedance, C_THZCE_PS_MEM, is equivalent to tHZCE for asynchronous SRAM and tEHQZ for FLASH in the respective memory device data sheets.
10.Output Enable high to data bus High Impedance, C_THZOE_PS_MEM, is equivalent to tHZOE for asynchronous SRAM and tGHQZ for FLASH in the respective memory device data sheets.
11.Write cycle time, C_TWC_PS_MEM, is equivalent to tWC for asynchronous SRAM and tCW for FLASH in the respective memory device data sheets.
12.Write cycle minimum pulse width, C_TWP_PS_MEM is equivalent to tWP for asynchronous SRAM and tPWE for FLASH in the respective memory device data sheets.
Read cycle Address Valid to Data Valid. (5,7) C_TAVDV_PS_MEM_x(1)
Read cycle Chip Enable high to Data Bus High Impedance. (8,9) C_THZCE_PS_MEM_x(1)
Read cycle Output Enable high to Data Bus High Impedance. (8,10) C_THZOE_PS_MEM_x(1)
Write cycle time (4,11) C_TWC_PS_MEM_x(1)
Write Enable minimum pulse width. (4,12) C_TWP_PS_MEM_x(1)
Write cycle Write Enable high to Data Bus Low Impedance. (13,14) C_TLZWE_PS_MEM_x(1)
Notes:
1.x = values for memory banks 0 to 3
2.This design can accommodate up to 4 banks of memory. The address range generics are designated as C_MEM0_BASEADDR, C_MEM1_BASEADDR, C_MEM0_HIGHADDR, C_MEM1_HIGHADDR, etc.
3.No default value will be specified for C_MEMx_BASEADDR, C_MEMx_HIGHADDR to insure that the actual value is set, i.e. if the value is not set, a compiler error will be generated. These generics must be a power of 2 and encompass the memory size for C_MEMx_BASEADDR, C_MEMx_HIGHADDR.
4.Write enable low time is the maximum of C_TWC_PS_MEM and C_TWP_PS_MEM.
5.Read cycle time is the maximum of C_TCEDV_PS_MEM and C_TAVDV_PS_MEM.
6.Chip Enable low to Data Valid, C_TCEDV_PS_MEM, is equivalent to tACE for asynchronous SRAM and tELQV for FLASH in the respective memory device data sheets.
7.Address Valid to Data Valid, C_TAVDV_PS_MEM, is equivalent to tAA for asynchronous SRAM and tAVQV for FLASH in the respective memory device data sheets.
8.Read cycle recovery to write is the maximum of C_THZCE_PS_MEM and C_THZOE_PS_MEM.
9.Chip Enable high to data bus High Impedance, C_THZCE_PS_MEM, is equivalent to tHZCE for asynchronous SRAM and tEHQZ for FLASH in the respective memory device data sheets.
10.Output Enable high to data bus High Impedance, C_THZOE_PS_MEM, is equivalent to tHZOE for asynchronous SRAM and tGHQZ for FLASH in the respective memory device data sheets.
11.Write cycle time, C_TWC_PS_MEM, is equivalent to tWC for asynchronous SRAM and tCW for FLASH in the respective memory device data sheets.
12.Write cycle minimum pulse width, C_TWP_PS_MEM is equivalent to tWP for asynchronous SRAM and tPWE for FLASH in the respective memory device data sheets.
Если Вам не сложно объясните как эти вреянки относительно друг друга расположены.
Заранее благодарен.
З.Ы. У меня дочь родилась все кто рядом с Магдебургом приглашаю отметить
