Цитата(Mozart @ Oct 9 2007, 09:45)

таймер в ISS не работает, проверено...
У меня пока тот же результат, но есть утверждения, что должен работать (вот два):
1.
http://forum.niosforum.com/forum/index.php?showtopic=322The iss supports simulation of the following peripherals:
. memory (ram/rom)
. avalon timer
. avalon jtag uart
. avalon uart
2.
http://forum.niosforum.com/forum/index.php?showtopic=5418"If any unsupported components are present in the system, the ISS displays a warning message at the start of the run or debug session. The ISS ignores writes to unsupported components during simulation. Reading from an unsupported component during simulation returns zero.
suported component list:
-All Nios II processor cores: Nios II/f, Nios II/s, Nios II/e
-Interval timer core
-JTAG UART core
-UART core
-On-chip memory (RAM/ROM)
-SDRAM controller core
-IDT71V416 SRAM (1 MB SRAM mounted on Nios development board)
-EPCS serial flash controller core, with limitations."
And here is aditonal limitations of ISS:
Simulations are functional only, and not cycle-accurate.
The ISS does not model Nios II instruction and data caches, and will not find bugs involving cache initialization, flushing, or bypassing.
The ISS does not support reading or writing tightly coupled memories connected to the Nios II processor.
The ISS does not support custom instructions.
3.
А это взято из Nios II IDE HelpInstruction Set Simulator (ISS)
The Nios II instruction set simulator (ISS) allows you to execute and debug Nios II programs in simulation on a host PC. The ISS simulates software executing on a Nios II processor core connected to a limited set of peripherals. The simulation is at the functional level, and all operations complete in one cycle. It is not a cycle-accurate simulation, and therefore performance benchmarking on the ISS gives optimistic results. On a modern Windows PC, the ISS runs at about 300K instructions per second when simulating code on the fast example design provided in the Nios II Embedded Design Suite.
The ISS can produce an execution trace. The trace output appears in the Console view, and you can optionally redirect it to a file. It is common to output trace data to a file, because trace tends to produce a large amount of information.
ISS-supported SOPC Builder components:
- All Nios II processor cores: Nios II/f, Nios II/s, Nios II/e
- Interval timer core
- JTAG UART core
- UART core
- On-chip memory (RAM/ROM)
- SDRAM controller core
- IDT71V416 SRAM (1 MB SRAM mounted on Nios development board)
- EPCS serial flash controller core, with limitations.
If any unsupported components are present in the system, the ISS displays a warning message at the start of the run or debug session. The ISS ignores writes to unsupported components during simulation. Reading from an unsupported component during simulation returns zero.
SOPC Builder system requirements:
The Nios II ISS simulates a Nios II processor system described by an SOPC Builder system file (.ptf). The Nios II ISS makes the following assumptions about the SOPC Builder system:
- SOPC Builder successfully generated the .ptf file.
- All memories with initialized content are initialized from one .elf file.
- The system contains exactly one Nios II CPU. The ISS does not support multiprocessor systems.
- The system has one clock domain.
- The system has one address map. (This is true for all Nios II systems created by SOPC Builder.)
ISS limitations:
- Simulations are functional only, and not cycle-accurate.
- The ISS does not model Nios II instruction and data caches, and will not find bugs involving cache initialization, flushing, or bypassing.
- The ISS does not support reading or writing tightly coupled memories connected to the Nios II processor.
- The ISS does not support custom instructions.
- The ISS models the Nios II ienable register as a complete 32-bit register. In hardware (both on a target board and in HDL simulation), all bits associated with unused interrupt inputs are always zero.
- The EPCS Serial Flash Controller core only supports boot-from-flash behavior. If the SOPC Builder system contains an EPCS Serial Flash Controller core, the simulation does not model the full behavior of the EPCS device. The ISS only models the first 1 Kbytes of the controller's register map as a block of ROM. In the case that the processor resets to the EPCS controller address (the typical boot-from-flash scenario), the simulation relies on the fact that RAMs are pre-initialized. Therefore, the controller's boot-loader does not need to copy code from EPCS memory to RAM. Instead, the controller simply jumps directly to RAM.