library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram is
generic(Amax     : integer:=3);
port (clk,Wr,WrArg,fixhit,RdEqual, RdMore,RdLess: in std_logic;
  af    : out std_logic_vector(Amax downto 0);
  a     : in std_logic_vector(Amax downto 0);
     di    : in std_logic_vector(31 downto 0);
      argo  : out std_logic_vector(31 downto 0);
     do    : out std_logic_vector(31 downto 0));
procedure foundCompS (R,arg:in std_logic_vector (31 downto 0);signal E,M,L:out std_logic)is
begin
if R=Arg then E<='1';else E<='0';end if;
if R>Arg then M<='1';else M<='0';end if;
if R<Arg then L<='1';else L<='0';end if;
end foundCompS;  
end ram;

architecture Behavioral of ram is
type ram_type is array ((2**(Amax+1)-1)downto 0) of std_logic_vector (31 downto 0);
signal R      : ram_type;
signal arg    : std_logic_vector(31 downto 0);
signal SEqual : std_logic_vector((2**(Amax+1)-1) downto 0);
signal SMore  : std_logic_vector((2**(Amax+1)-1) downto 0);
signal SLess  : std_logic_vector((2**(Amax+1)-1) downto 0);
signal CMD   : std_logic_vector(5 downto 0);
begin
process(clk)
variable M_var : std_logic_vector((2**(Amax+1)-1)downto 0);
variable T     : std_logic;
variable Equal : std_logic_vector((2**(Amax+1)-1)downto 0);
variable More  : std_logic_vector((2**(Amax+1)-1)downto 0);
variable Less  : std_logic_vector((2**(Amax+1)-1)downto 0);
begin
CMD<=(Wr,WrArg,FixHit,RdEqual,RdMore,RdLess);
    if (clk'event and clk = '1') then
 case CMD is
 when ("100000") =>R(conv_integer(a)) <= di;
[B]--  when ("010000") =>arg<=di;[/B]--после синтеза это набор D-тр
 when ("001000") =>Equal:=SEqual;More:=SMore;Less:=SLess;
 when ("000100") =>T:='0';
     for i in 0 to (2**(Amax+1)-1) loop
     if Equal(i)='1' then T:='1';af<=CONV_STD_LOGIC_VECTOR (i, Amax+1);
     Equal(i):='0';end if;
     exit when T='1';
     end loop;
 when ("000010") =>T:='0';
     for i in 0 to (2**(Amax+1)-1) loop
     if More(i)='1' then T:='1';af<=CONV_STD_LOGIC_VECTOR (i, Amax+1);
     More(i):='0';end if;
     exit when T='1';
     end loop;
 when ("000001") =>T:='0';
     for i in 0 to (2**(Amax+1)-1) loop
     if Less(i)='1' then T:='1';
     af<=CONV_STD_LOGIC_VECTOR (i, Amax+1);
     Less(i):='0';end if;
     exit when T='1';
     end loop;
 when others =>null;
 end case;
end if;
end process;
forM:for i in 0 to (2**(Amax+1)-1)generate
  foundCompS(R(i),Arg,SEqual(i),SMore(i),SLess(i));    
end generate forM;
argo<=arg;--введено для контроля потом выкину
[B]Arg<=Di when WrArg='1';[/B] --после синтеза это превращается в защёлку
do <= R(conv_integer(a));
end Behavioral;