MODULE    ?RESET
        COMMON    INTVEC:CODE:NOROOT(2)
        PUBLIC  __program_start
        EXTERN    ?cstartup
        EXTERN    undef_handler, swi_handler, prefetch_handler
        EXTERN    data_handler,irq_handler, fiq_handler
        CODE32; Always ARM mode after reset    
        org    0x00
__program_start
        ldr    pc,=?cstartup; Absolute jump can reach 4 GByte
        org    0x04
        ldr    pc,=undef_handler
        org    0x08
;        ldr    pc,=swi_handler
        org    0x0c
        ldr    pc,=prefetch_handler
        org    0x10
        ldr    pc,=data_handler
                org     0x14
                DCD     0x00000000
        org    0x18
        ldr    pc,=irq_handler
        org    0x1c
        ldr    pc,=fiq_handler

; Constant table entries (for ldr pc) will be placed at 0x20
        org    0x20
        LTORG
                ENDMO

        org    0x18
        ldr    pc,=irq_handler

LDR (ARM) LDR{condition} register,=expression1
or
LDR{condition} register,expression2
Parameters
Description
The first form of the LDR pseudo-instruction loads a register with any 32-bit
expression. The second form of the instruction reads a 32-bit value from an address
specified by the expression. Note that there is also a true LDR instruction.
If the value of expression1 is within the range of a MOV or MVN instruction, the
assembler generates the appropriate instruction. If the value of expression1 is not
within the range of a MOV or MVN instruction, or if the expression1 is unsolved, the
assembler places the constant in a literal pool and generates a program-relative LDR
instruction that reads the constant from the literal pool. The offset from the program
location counter to the constant must be less than 4 Kbytes. See also the LTORG
directive in the section Assembler control directives, page 80, for more information.
Example
LDR r1,=0x12345678; => LDR r1,[pc,#4]
; loads 0x12345678 from the
; literal pool into r1
LDR r2,my_data; loads 0xFFEEDDCC into r2
; => LDR r2,[pc,#-4]
DATA
my_data DC32 0xFFEEDDCC
LTORG
condition An optional condition code.
register The register to be loaded.
expression1 Any 32-bit expression.
expression2 A program location counter-relative expression in the range -4087 to
+4103 from the program location counter.


LDR (CODE16) LDR register, =expression1
or
LDR register, expression2
Parameters
Description
As in ARM mode, the first form of the LDR pseudo-instruction in Thumb mode loads
a register with any 32-bit expression. The second form of the instruction reads a 32-bit
value from an address specified by the expression. However, the offset from the
program location counter to the constant must be positive and less than 1 Kbyte.
Example
LDR r1,=ext_label; => LDR r1,[pc,#8]
; loads ext_label from the
; literal pool into r1
NOP
LDR r2,my_data; loads 0xFFEEDDCC into r2
NOP; => LDR r2,[pc,#0]
DATA
my_data DC32 0xFFEEDDCC
LTORG
register The register to be loaded. LDR can access the low registers (R0–R7) only.
expression1 Any 32-bit expression.
expression2 A program location counter-relative expression +4 to +1024 from the
program location counter.


LDR (THUMB) LDR{condition} register,=expression
Parameters
Description
Similar to the LDR (CODE16) instruction, but by using a 32-bit instruction, a larger
value can be loaded directly with a MOV or MVN instruction without requiring the
constant to be placed in a literal pool.
If only 16-bit Thumb instructions are available, see LDR (CODE16), page 104.
By specifying a 16-bit version explicitly with the LDR.N instruction, a 16-bit
instruction is always generated. This may lead to the constant being placed in the
literal pool, even though a 32-bit instruction could have loaded the value directly using
MOV or MVN.
By specifying a 32-bit version explicitly with the LDR.W instruction, a 32-bit
instruction is always generated.
If you do not specify either .N or .W, the 16-bit LDR (CODE16) instruction will be
generated, unless Rd is R8-R15, which leads to the 32-bit variant being generated.
Note: The syntax LDR{condition} register, expression2, as described for
LDR (ARM) and LDR (CODE16), is no longer considered a pseudo-instruction. It is
part of the normal instruction set as specified in the Unified Assembler syntax from
Advanced RISC Machines Ltd.
condition An optional condition code if the instruction is placed after an IT
instruction.
register The register to be loaded.
expression Any 32-bit expression.