AT91C_BASE_PIOA->PIO_PDR=(1<<11)|(1<<10);  
  AT91C_BASE_PIOA->PIO_MDER=(1<<11)|(1<<10);
  AT91C_BASE_PIOA->PIO_PPUDR=(1<<11)|(1<<10);
  AT91C_BASE_PIOA->PIO_ASR=(1<<11)|(1<<10);
    
  AT91F_TWI_CfgPMC();

  AT91C_BASE_TWI->TWI_CR=(AT91C_TWI_SWRST); //сброс, так и не понял для чего он нужен

  AT91C_BASE_TWI->TWI_CWGR=(1<<16)|(200<<8)|(200<<0); //МСК=47 МГц
  AT91C_BASE_TWI->TWI_CR=AT91C_TWI_MSEN;
  AT91C_BASE_TWI->TWI_MMR=(44<<16);       // у потенциометра 7ми битный адрес 44  

  AT91C_BASE_TWI->TWI_THR=0x24; //Первый регистр пошёл
  AT91C_BASE_TWI->TWI_CR=(AT91C_TWI_START);
  while(!(AT91C_BASE_TWI->TWI_SR&AT91C_TWI_TXRDY)); //А вот с TWI_SR какая-то хрень
  AT91C_BASE_TWI->TWI_THR=0xFF; //Второй регистр пошёл
  while(!(AT91C_BASE_TWI->TWI_SR&AT91C_TWI_TXRDY));  

  AT91C_BASE_TWI->TWI_CR=(AT91C_TWI_STOP);    
  while(!(AT91C_BASE_TWI->TWI_SR&AT91C_TWI_TXCOMP));

// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed
#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)
#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)
#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)
#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged
#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)
#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer
#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer
#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt
#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt