Эхх...
test.s:493: Error: registers may not be the same -- `strexb r0,r0,[r1]'
test.s:517: Error: registers may not be the same -- `strexh r0,r0,[r1]'
test.s
Код
.align 1
.global __STREXB
.thumb
.thumb_func
.type __STREXB, %function
__STREXB:
.LFB19:
.loc 1 733 0
.cfi_startproc
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
.LVL34:
.loc 1 736 0
@ 736 "c:/gcc/lib/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c" 1
strexb r0, r0, [r1] <-- 493 line
@ 0 "" 2
.LVL35:
.loc 1 738 0
.thumb
bx lr
.cfi_endproc
.LFE19:
.size __STREXB, .-__STREXB
.align 1
.global __STREXH
.thumb
.thumb_func
.type __STREXH, %function
__STREXH:
.LFB20:
.loc 1 750 0
.cfi_startproc
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
.LVL36:
.loc 1 753 0
@ 753 "c:/gcc/lib/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c" 1
strexh r0, r0, [r1] <-- 517 line
А это исходный текст
Код
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
A.3.8 LDREX and STREX
Load and Store Register Exclusive.
Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where
cond is an optional condition code; see “Conditional Execution” section on page 358.
Rd is the destination register for the returned status.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the value in Rn.
Restrictions
In these instructions:
- Do not use PC.
- Do not use SP for Rd and Rt.
- For STREX, Rd must be different from both Rt and Rn.
- The value of offset must be a multiple of 4 in the range 0–1020.
Вызов принят.
описания какие-то вялые везде.
)
Только тогда и под венду (можно 32) тоже