Цитата(okela @ Apr 18 2005, 10:07)
Частота кварца 12 МГц. Пробовал ставить и меньше и больше..
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А HELP почитать?
Convergence Problems
· Timestep too small. This means that the circuit has switched in such a way that advancing the time even by very small amounts (typically 1E-18s) still does not produce an acceptably small change in circuit voltages.
Often, this is caused by a badly designed model, or by not supplying sufficient parameters to a diode or transistor model. In a particular, if the junction capacitance values are not chosen correctly, these devices will exhibit zero switching times which can lead directly to this error message.
Most convergence errors are due to badly drawn circuits or incorrect models - time after time we have had circuits sent in that ‘won’t simulate’ only to find that something isn’t connected. Please check the simulation log for clues, and re-check your circuit before jumping to the conclusion that PROSPICE is at fault. Where 3rd party SPICE or VSM models have been used, we cannot spend time debugging them unless you can supply a simple circuit demonstrating the problem.
Beware also of using 3rd party SPICE models which use features not supported in standard SPICE 2 or SPICE 3. Models developed for PSPICE™ can include all manner of elements and syntax constructs that are not standard SPICE.
Oscillators cause special problems because the initial solution for the operating point will fail. After all, an oscillator has no steady state! Use IC , NS or OFF properties to define a starting state as discussed under INITIAL CONDITIONS.
If the problem really is numerical convergence, you can try the following tactics:
· Increase the value of GMIN. This is a leakage resistance for reverse biased semiconductor junctions, and lower values make the circuit look more and more like a network of resistors (which will always solve). But this is at the expense of accuracy. The default is 1E-12; values above 1E-9 will give fairly meaningless results.Note in any case, that SPICE3F5 will try what is called GMIN stepping if at first the circuit will not converge. This means that a large GMIN is used to find an initial solution, and the value is then ramped back to its original value in order to maintain accuracy.
· Increase the value of ABSTOL and/or RELTOL. These values control the accuracy that is required for the simulation to be deemed to have converged. However, the larger you make these tolerances, the less accurate the results will actually be.
· If the circuit uses op-amps, try specifying MODFILE=OA_IDEAL instead of a specific device type - this model is much easier to simulate.
· Lower the value of TRTOL. This will make SPICE use smaller timesteps so it will be less likely to ‘lose
’ a convergent solution, but at the expense of longer run times. This will only work if the simulation has failed part way through a transient analysis.
· You should also try reducing TRTOL if plotted traces look ‘spiky’, or contain mathematical noise. This often manifests itself as oscillation of a value after a rapid level transition.
