library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.constants.all;        --library containing package of constants of TFT LCD timing and other ADU related parameters

entity TFT_IPG is
port (
    nRST, CLK: in std_logic;
    EXT_VIDEO_DATA: in std_logic_vector(17 downto 0);    --external video data input
    VIDEO_INPUT: in std_logic;                            --IDG video pattern input config.
    IPG_PATTERN: in std_logic;                            --IDG video pattern type config.
    
    HSYNC_TFT, VSYNC_TFT, ENAB_TFT: out std_logic;        --TG syncs output to TFT
    DATA_TFT: out std_logic_vector(17 downto 0)            --DG data output to TFT
    );
end entity;

architecture TFT_IPG_arch of TFT_IPG is

    component TFT_TG
        port (nRST, CLK: in std_logic;
              HSYNC, VSYNC, ENAB: out std_logic;
              active_video_flag: out boolean;
              line_cnt_out: out natural range 0 to TH
             );
    end component;
    
    component TFT_DG
        port (nRST, CLK, PATTERN_TYPE: in std_logic;
              HSYNC, VSYNC, ENAB: in std_logic;
              active_video_flag: in boolean;
              --color_switch_debug: out std_logic;    --for debug only
              line_cnt: in natural range 0 to TH;
              DATA_OUT: out std_logic_vector(17 downto 0)
             );
    end component;
    
    signal HSYNC_sig, VSYNC_sig, ENAB_sig: std_logic;
    signal act_v_flag: boolean;
    signal l_cnt: natural range 0 to TH;
    signal data_switch: std_logic;
    signal DATA_sig: std_logic_vector(17 downto 0);
    
begin
    TFT_TG_inst: TFT_TG port map(nRST => nRST, CLK => CLK, HSYNC => HSYNC_sig, VSYNC => VSYNC_sig, ENAB => ENAB_sig, active_video_flag => act_v_flag, line_cnt_out => l_cnt);
    TFT_DG_inst: TFT_DG port map(nRST => nRST, CLK => CLK, PATTERN_TYPE => IPG_PATTERN, HSYNC => HSYNC_sig, VSYNC => VSYNC_sig, ENAB => ENAB_sig, active_video_flag => act_v_flag, line_cnt => l_cnt, DATA_OUT => DATA_sig);
    
    HSYNC_TFT <= HSYNC_sig;    --pass through HSYNC from TFT_TG to IPG output
    VSYNC_TFT <= VSYNC_sig; --pass through VSYNC from TFT_TG to IPG output
    ENAB_TFT <= ENAB_sig;   --pass through ENAB from TFT_TG to IPG output
    DATA_TFT <= DATA_sig when data_switch = '1' else EXT_VIDEO_DATA;
    
    process(nRST, CLK)        --reading video input config. input during Reset while clock is present
    begin
        if CLK'event and CLK = '1' the
            if nRST = RST_pol then
                data_switch <= VIDEO_INPUT;
            else
                data_switch <= data_switch;
            end if;
        end if;
    end process;
    
    --process(data_switch)
    --begin
        
            --if data_switch = '1' then
                --DATA_TFT <= DATA_sig;
            --else
                --DATA_TFT <= EXT_VIDEO_DATA;
            --end if;
        
    --end process;
end;

DATA_TFT <= DATA_sig when data_switch = '1' else EXT_VIDEO_DATA;

--process(data_switch)
    --begin
        
            --if data_switch = '1' then
                --DATA_TFT <= DATA_sig;
            --else
                --DATA_TFT <= EXT_VIDEO_DATA;
            --end if;
        
    --end process;

ata_switch <= VIDEO_INPUT

process(data_switch, DATA_sig, EXT_VIDEO_DATA)
begin
  if data_switch = '1' then
    DATA_TFT <= DATA_sig;
  else
    DATA_TFT <= EXT_VIDEO_DATA;
  end if;
end process;

process(nRST, CLK)        --reading video input config. input during Reset while clock is present
begin
  if CLK'event and CLK = '1' the
    if nRST = RST_pol then
      data_switch <= VIDEO_INPUT;
--    else
--      data_switch <= data_switch;
    end if;
  end if;
end process;

process(nRST, CLK)        --reading video input config. input during Reset while clock is present
begin
  if CLK'event and CLK = '1' the
    if nRST = RST_pol then
        data_switch <= VIDEO_INPUT;
    else
        data_switch <= data_switch;
    end if;
  end if;
end process;