/* Remap internal SRAM to 0x00000000 */
memwrite 4 0xFFFFED00 0x3

//****************************************************************
// Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
memwrite 4 0xFFFFFD44 0x00008000

//***********************************************************************
//Initialize main oscillator
//#define BOARD_OSCOUNT           (AT91C_CKGR_OSCOUNT & (64 << 8))
//AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
memwrite 4 0xFFFFFC20 0x00003F01
//while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
__sleep -m 500

/* Initialize PLLA at 200MHz (198.656) */
//   AT91C_BASE_CKGR->CKGR_PLLAR = BOARD_CKGR_PLLA
//                                | BOARD_PLLACOUNT
//                                | BOARD_MULA
//                                | BOARD_DIVA;
//(AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2)| (63 << 8) | (0x6D << 16) | 9
memwrite 4 0xFFFFFC28 0x206DBF09
//while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
__sleep -m 500

///* Switch to main oscillator + prescaler */
//    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_MDIV_2;
memwrite 4 0xFFFFFC30 0x00000100
//while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
__sleep -m 500

/* Switch to PLL + prescaler */
//    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_MDIV_2 | AT91C_PMC_CSS_PLLA_CLK;
memwrite 4 0xFFFFFC30 0x00000102
//while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
__sleep -m 500

//*********************************************************************
//Set SDRAM for works at 100 MHz

//Enable clock PIOA- PIOE
//pPMC->PMC_PCDR = periphIds;
memwrite 4 0xFFFFFC10 0x0000001C

//Configure PIOD as peripheral (D16/D31)
// pPio->PIO_ASR = periphAEnable;
memwrite 4 0xfffff870 0xffff0000
// pPio->PIO_BSR = periphBEnable;
memwrite 4 0xfffff874 0x00000000
// pPio->PIO_PDR = (periphAEnable | periphBEnable);
memwrite 4 0xfffff804 0xffff0000

// Init MATRIX to support EBI0 CS1 for SDRAM
//AT91C_BASE_CCFG->CCFG_EBI0CSA |= AT91C_EBI_CS1A_SDRAMC;
memwrite 4 0xFFFFED20 0x00000001

//Init SDRAM A minimum pause of 200us is provided to precede any signal toggle
//    AT91C_BASE_SDRAMC0->SDRAMC_CR = (AT91C_SDRAMC_TXSR_8 | AT91C_SDRAMC_TRAS_5 |\
//                     AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRP_2 |\
//                     AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TWR_2 |\
//                     AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 |\
//                     AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_CAS_2 |\
//                     AT91C_SDRAMC_DBW_32_BITS);
memwrite 4 0xFFFFE208 0x85227259
__sleep -m 200

//A Precharge All command is issued to the SDRAM
//    AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_PRCGALL_CMD;
memwrite 4 0xFFFFE200 0x00000002
//*    *AT91C_SDRAM    = 0x00000000
memwrite 4 0x20000000 0x00000000

//Eight Auto-refresh are provided
//AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD;
memwrite 4 0xFFFFE200 0x00000004

memwrite 4 0x20000000 0x00000000
memwrite 4 0x20000000 0x00000000
memwrite 4 0x20000000 0x00000000
memwrite 4 0x20000000 0x00000000
memwrite 4 0x20000000 0x00000000
memwrite 4 0x20000000 0x00000000
memwrite 4 0x20000000 0x00000000
memwrite 4 0x20000000 0x00000000

//A mode register cycle is issued to program the SDRAM parameters
//    AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD;
memwrite 4 0xFFFFE200 0x00000003
//*(pSDRAM+0x20) = 0;
memwrite 4 0x20000020 0xCAFEDEDE

//Write refresh rate into SDRAMC refresh timer COUNT register
//AT91C_BASE_SDRAMC0->SDRAMC_TR = AT91C_SDRAMC_COUNT & 0x65B;
memwrite 4 0xFFFFE204 0x65B

// A Normal Mode Command is provided, 3 clocks after tMRD is set"
//AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD;
memwrite 4 0xFFFFE200 0x00000000
// *pSDRAM = 0
memwrite 4 0x20000000 0x00000000