Имеется плата от Инструментальных систем, на ней установлен АЦП и DDC GC4016. Фильтры создаю программой LabGrayChip от ИнСиса. Необходимо теоретически рассчитать время прохождения сигнала от входа DDC до его выхода. В документации нашел вот это. Задержку в тактах считать относительно входной тактовой частоты ? И как в LabGrayChip посмотреть длину фильтров ?
The data latency through the chip is defined as the delay
from the rising edge of a step function input to the chip to the
rising edge of the step function as it leaves the chip. This
delay is dominated by the number of taps in each of the
filters. An estimate of the overall latency through the chip,
expressed as the number of input clock cycles is:
(CIC latency = 2.5N) + (CFIR latency = 0.5N*CTAP) +
(PFIR latency = N*PTAP) + (Resampler latency =
2N*NMULT) + (Output delay) + (Pipeline delay)
where N is the CIC decimation ratio, CTAP is the number of
CFIR taps, and PTAP is the number of PFIR taps. CTAP and
PTAP are normally 21 and 63. Latency can be reduced by
using the NO_SYM_CFIR and NO_SYM_PFIR modes to
shorten these filters. The latency in the resampler can be
minimized by using the bypass configuration (See Section
3.5.6).
The Output delay depends upon the output mode, but is
approximately equal to the fifo block size (BLOCK_SIZE+1)
times the output’s sample period. The Pipeline delay is
approximately 40 clock cycles.