library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.tx_dvbt.all;  

entity CIC_filtr is
port
(
        reset:   in std_logic;
        clk:     in std_logic;     
        
        in_re:  in std_logic_vector(11 downto 0);
        in_im:  in std_logic_vector(11 downto 0);
        in_ena: in std_logic;
                
        out_re: out std_logic_vector(15 downto 0);
        out_im: out std_logic_vector(15 downto 0)
                
);
end CIC_filtr;

architecture cic_a of CIC_filtr is
     constant P: integer:=3; -- CIC order

     type tWordArray is array (integer range<>) of std_logic_vector(15 downto 0);
    
     signal dstages_re: tWordArray(0 to P-1);
     signal dstages_im: tWordArray(0 to P-1);
    
     signal astages_re: tWordArray(0 to P);
     signal astages_im: tWordArray(0 to P);
         
     signal outd_re:  tWordArray(0 to P);
     signal outd_im:  tWordArray(0 to P);
    
    
    
begin
    G1:
    for k in 0 to P-1 generate
            sub16re_insts:
            sub16 port map
            (
                    aclr => reset,
                    clock => clk,
                    dataa => outd_re(k),
                    datab    => dstages_re(k),
                    result=> outd_re(k+1)
            );
            
            sub16im_insts:
            sub16 port map
            (
                aclr => reset,
                    clock => clk,
                    dataa => outd_im(k),
                    datab    => dstages_im(k),
                    result=> outd_im(k+1)
            );
            
            acc16re_insts:
            acc16 port map
            (
                aclr => reset,             
                    clock => clk,
                    data=> astages_re(k),  
                    result=> astages_re(k+1)
            );

            acc16im_insts:
            acc16 port map
            (
            aclr => reset,             
                clock => clk,
                data=> astages_im(k),  
                result=> astages_im(k+1)
            );
            
    end generate G1;


        diff_stages:
        process(clk, reset)
        begin
            if reset='1' then
                
                for i in 0 to P-1 loop
                    dstages_re(i)<=(others=>'0');                 
                    dstages_im(i)<=(others=>'0');                                     
        --            astages_re(i)<=(others=>'0');                 
        --            astages_im(i)<=(others=>'0');                                         
                end loop;
                                
                outd_re(0) <= (others=>'0');
                outd_im(0) <= (others=>'0');
                
            else
            
                if in_ena='0' then
                    null;
                elsif rising_edge(clk) then
                
                    outd_re(0) <= in_re(11)&in_re(11)&in_re(11)&in_re(11)&in_re;
                    outd_im(0) <= in_im(11)&in_im(11)&in_im(11)&in_im(11)&in_im;
                    
                    for i in 0 to P-1 loop
                         dstages_re(i) <= outd_re(i);
                         dstages_im(i) <= outd_im(i);                          
                    end loop;    
                    
                    
                end if;
                
            end if;    
        end process;
        
        astages_re(0) <= outd_re(P) when in_ena='1' else
                                         (others=>'0');     
        
        astages_im(0) <=  outd_im(P) when in_ena='1' else
                                         (others=>'0');     
        
        out_re <= astages_re(P);
        out_im <= astages_im(P);
        
end architecture cic_a;