Есть такой код:
Код
hf_dep1: process (half_full,signal2foto) is
begin
if ( half_full'event and half_full='1' ) then --аналогично (rising_edge(half_full)) then
---+++
rd <= '1';
rd_clk <= clock;
---+++
end if;
if ( signal2foto'event and signal2foto='1' ) then --аналогично (rising_edge(signal2foto)) then
---+++
rd <= '0';
rd_clk <= '0';
---+++
end if;
end process;
begin
if ( half_full'event and half_full='1' ) then --аналогично (rising_edge(half_full)) then
---+++
rd <= '1';
rd_clk <= clock;
---+++
end if;
if ( signal2foto'event and signal2foto='1' ) then --аналогично (rising_edge(signal2foto)) then
---+++
rd <= '0';
rd_clk <= '0';
---+++
end if;
end process;
и ему подобный
Код
reset_proc: process (rst,start) is
begin
if ( (rst'event and rst='1') and start='0' ) then --аналогично (rising_edge(rst) and start='0') then
--+++
in_rst_signal <= '1';
--+++
end if;
if ( start'event and start='1' ) then --аналогично (rising_edge(start)) then
--+++
in_rst_signal <= '0';--return back reset signal to ZERO
rst <= '0';
--+++
end if;
end process;
begin
if ( (rst'event and rst='1') and start='0' ) then --аналогично (rising_edge(rst) and start='0') then
--+++
in_rst_signal <= '1';
--+++
end if;
if ( start'event and start='1' ) then --аналогично (rising_edge(start)) then
--+++
in_rst_signal <= '0';--return back reset signal to ZERO
rst <= '0';
--+++
end if;
end process;
Матюкаеться так
:Цитата
Error (10820): Netlist error at my_fifo.vhd(148): can't infer register for in_rst_signal because its behavior depends on the edges of multiple distinct clocks
Error (10820): Netlist error at my_fifo.vhd(112): can't infer register for rd_clk because its behavior depends on the edges of multiple distinct clocks
Error (10820): Netlist error at my_fifo.vhd(112): can't infer register for rd because its behavior depends on the edges of multiple distinct clocks
Error (10820): Netlist error at my_fifo.vhd(112): can't infer register for rd_clk because its behavior depends on the edges of multiple distinct clocks
Error (10820): Netlist error at my_fifo.vhd(112): can't infer register for rd because its behavior depends on the edges of multiple distinct clocks
В принципе могу понатыкивать компонентов с библиотек и посоединять их как нужнов коде, но есть желание разобраться с VHDL - а то как то я его знаю со схематической стороны
Что же я не так делаю ?
--
Имею книженцию <Суворова,Шейнин..> - по ней и выучил азы
)) 
