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Полная версия этой страницы: ЕДК 9.2.02i помогите новичку с 3 проблеммами
Форум разработчиков электроники ELECTRONIX.ru > Программируемая логика ПЛИС (FPGA,CPLD, PLD) > Работаем с ПЛИС, области применения, выбор
Serg`
Доброе время суток!!!!

Сразу к делу!! Я сейчас создаю cвой хардовый проект (он находится на прикрепленных файлах с 1 по 13, на 14 рисунке представленны все адреса) в ЕДК 9.2.02i под Xilinx S3 xc3s4000 с не очень то большой периферией (она приведена на рисунках) и уже 3 день бьюсь с непонятными ошибками!!! Следующего типа:


1) Проблема с шиной iLMB!!Причем я проект е трогал вообще тока создал и нажал апдэйт битстрим и получил при разводке следующий лог:

I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[1].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[0].TCSR0_FF
_I' has unconnected output pin
ERROR:NgdBuild:455 - logical net 'ilmb_LMB_BE<0>' has multiple driver(s):
pin G on block XST_GND with type GND,
pin PAD on block lmb_bram/lmb_bram/ilmb_LMB_BE<0> with type PAD
ERROR:NgdBuild:924 - input pad net 'ilmb_LMB_BE<0>' is driving non-buffer
primitives:

pin G on block XST_GND with type GND,
pin I0 on block
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/dbg_stop_i_not00
011 with type LUT3,
pin I0 on block
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/Want_to_Stop_not
00011 with type LUT4,
pin I3 on block
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/dbg_stop_i_mux00
001 with type LUT4,
pin I3 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en4 with type LUT4,
pin I0 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en15 with type LUT4,
pin I0 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en4 with type LUT4,
pin I1 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en4 with type LUT4,
pin I2 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en4 with type LUT4,
pin I2 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en12 with type LUT4,
pin I3 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en12 with type LUT4,
pin I1 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en15 with type LUT4,
pin I2 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en15 with type LUT4,
pin I1 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARB
ITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en12 with type LUT4,
pin I0 on block
mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/Set_Cnt_on_plb2o
pb_rearb_en12 with type LUT4,
pin I0 on block ilmb_cntlr/ilmb_cntlr/lmb_we_3_and00001 with type LUT3,
pin I2 on block ilmb_cntlr/ilmb_cntlr/lmb_we_2_and00001 with type LUT3,
pin I2 on block ilmb_cntlr/ilmb_cntlr/lmb_we_1_and00001 with type LUT3,
pin I2 on block ilmb_cntlr/ilmb_cntlr/lmb_we_0_and00001 with type LUT3,
pin I0 on block ilmb_cntlr/ilmb_cntlr/lmb_we_0_and00001 with type LUT3
WARNING:NgdBuild:452 - logical net 'N38' has no driver
WARNING:NgdBuild:452 - logical net 'N39' has no driver
WARNING:NgdBuild:452 - logical net 'N40' has no driver
WARNING:NgdBuild:452 - logical net 'N41' has no driver
WARNING:NgdBuild:452 - logical net 'N42' has no driver
WARNING:NgdBuild:452 - logical net 'N43' has no driver
WARNING:NgdBuild:452 - logical net 'N44' has no driver
WARNING:NgdBuild:452 - logical net 'N45' has no driver
WARNING:NgdBuild:452 - logical net 'N46' has no driver
WARNING:NgdBuild:452 - logical net 'N47' has no driver
WARNING:NgdBuild:452 - logical net 'N48' has no driver
WARNING:NgdBuild:452 - logical net 'N49' has no driver
WARNING:NgdBuild:452 - logical net 'N50' has no driver
WARNING:NgdBuild:452 - logical net 'N51' has no driver
WARNING:NgdBuild:452 - logical net 'N52' has no driver
WARNING:NgdBuild:452 - logical net 'N53' has no driver
WARNING:NgdBuild:452 - logical net 'N54' has no driver
WARNING:NgdBuild:452 - logical net 'N55' has no driver
WARNING:NgdBuild:452 - logical net 'N56' has no driver
WARNING:NgdBuild:452 - logical net 'N57' has no driver
WARNING:NgdBuild:452 - logical net 'N58' has no driver
WARNING:NgdBuild:452 - logical net 'N59' has no driver
WARNING:NgdBuild:452 - logical net 'N60' has no driver
WARNING:NgdBuild:452 - logical net 'N61' has no driver
WARNING:NgdBuild:452 - logical net 'N62' has no driver
WARNING:NgdBuild:452 - logical net 'N63' has no driver
WARNING:NgdBuild:452 - logical net 'N64' has no driver
WARNING:NgdBuild:452 - logical net 'N65' has no driver
WARNING:NgdBuild:452 - logical net 'N66' has no driver
WARNING:NgdBuild:452 - logical net 'N67' has no driver
WARNING:NgdBuild:452 - logical net 'N68' has no driver
WARNING:NgdBuild:452 - logical net 'N69' has no driver
WARNING:NgdBuild:452 - logical net 'N70' has no driver
WARNING:NgdBuild:452 - logical net 'N71' has no driver
WARNING:NgdBuild:452 - logical net 'N72' has no driver
WARNING:NgdBuild:452 - logical net 'N73' has no driver
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
debug_module/debug_module/BUFG_DRCK1 drives no clock pins

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 2
Number of warnings: 96


One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...

make: *** [__xps/system_routed] Error 1
Done!



Не могу понять откуда взялся этот общий доступ к 0 разряду этой шины!!Ведь я сам ничего туда не заводил!!



2)Если поменять тип памяти с сгенерированного на тот который нужен мне то получаю следующий лог:



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
ERROR:MDT - issued from TCL procedure "check_icache_fsl" line 86
microblaze_0 (microblaze) - ICACHE address space [0x8C000000:0x8FFFFFFF]
does not match IP "DDR_SDRAM_MT46V16M16_5B" on bus "ixcl"

INFO:coreutil - License for component <xps_ethernetlite_v1> allows you to use
this component, and also grants you access to the source code used to
implement this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.


Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: The Generic_Ethernet_10_100 core has constraints automatically generated
by XPS in
implementation/generic_ethernet_10_100_wrapper/generic_ethernet_10_100_wrapper.u
cf.
It can be overridden by constraints placed in the system.ucf file.

INFO: The DDR_SDRAM_MT46V16M16_5B core has constraints automatically generated
by XPS in
implementation/ddr_sdram_mt46v16m16_5b_wrapper/ddr_sdram_mt46v16m16_5b_wrapper.u
cf.
It can be overridden by constraints placed in the system.ucf file.

ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
Done!



хотя HIGHADDRES для ДДР у меня совсем другой!!



3)И последнее если после всего вообще удалить ДДРку то возникает последняя и напрочь убивающая меня ошибка:



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
ERROR:MDT - issued from TCL procedure "check_icache_fsl" line 152
microblaze_0 (microblaze) - The ICACHE XCL bus interface is unconnected. The
MicroBlaze processor (version v5.00.a and higher) requires that the XCL bus
interface is connected when the ICACHE is enabled.

INFO:coreutil - License for component <xps_ethernetlite_v1> allows you to use
this component, and also grants you access to the source code used to
implement this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.

INFO:coreutil - License for component <xps_uart16550_v1> allows you to use this
component, and also grants you access to the source code used to implement
this component.


Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: The Generic_Ethernet_10_100 core has constraints automatically generated
by XPS in
implementation/generic_ethernet_10_100_wrapper/generic_ethernet_10_100_wrapper.u
cf.
It can be overridden by constraints placed in the system.ucf file.

ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
Done!

Что за шина такая!!Объясните!!



В общем вот 3 моих умопомрачительных проблемы!!Подскажите как с ними справится или хотя бы дайте направления для их решения!!!! help.gif smile3046.gif maniac.gif 07.gif



И кстати там по умолчанию стоят DDR_SDRAM_MT64V16M16_5B, а мне нужно DDR_SDRAM_MT64V16M32_5B сразу можно их прописать как-нибудь а не потом настраивать??
help.gif help.gif


RKOB
1 - адреса сгинерены не верно (у вас и ддр контроллер и лмб имеют одинаковый базовый адрес)
2 - зачем вам XCL PLB ?
Измените базовый адрес и запустите generate address , а затем либген (generate libs)... Удачи!
Serg`
Насчет XCL я не знаю я ее не добавлял! Проект создан с помощью визарда!!

А за адреса спасибо сейчас буду пробывать!!

П.С. Если не тяжело обясните что это за шина такая XCL!

Зарание спасибо!!!!!
Serg`
Я перегенерировал адреса!! Очистил хардвар!! Урезал всю переферию до минимума!! Запустил лбген, но всеравно та же ошибка!!!!
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