*addr = data

BEGIN plb_ddr
PARAMETER INSTANCE = DDR_SDRAM_16Mx32
PARAMETER HW_VER = 1.11.a
PARAMETER C_PLB_CLK_PERIOD_PS = 10000
PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 80000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 15000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_TREFI = 7800000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 9
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_DDR_DWIDTH = 32
PARAMETER C_MEM0_BASEADDR = 0x00000000
PARAMETER C_MEM0_HIGHADDR = 0x03ffffff
BUS_INTERFACE SPLB = plb
PORT PLB_Clk = sys_clk_s
PORT DDR_Addr = fpga_0_DDR_SDRAM_16Mx32_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_16Mx32_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_SDRAM_16Mx32_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_SDRAM_16Mx32_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_SDRAM_16Mx32_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_SDRAM_16Mx32_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_SDRAM_16Mx32_DDR_WEn
PORT DDR_DM = fpga_0_DDR_SDRAM_16Mx32_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_16Mx32_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_16Mx32_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_SDRAM_16Mx32_DDR_Clk
PORT DDR_Clkn = fpga_0_DDR_SDRAM_16Mx32_DDR_Clkn
PORT Clk90_in = clk_90_s
PORT Clk90_in_n = clk_90_n_s
PORT PLB_Clk_n = sys_clk_n_s
# clk feedback shifted 90
PORT DDR_Clk90_in = internal_feedback
# not
PORT DDR_Clk90_in_n = internal_feedback_n
END

BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM_16Mx32
PARAMETER HW_VER = 3.00.a
PARAMETER C_MEM_PARTNO = CUSTOM
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
PARAMETER C_MEM_CLK_WIDTH = 1
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_MEM_CS_N_WIDTH = 1
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
PARAMETER C_MPMC_HIGHADDR = 0x03FFFFFF
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_PIM1_BASETYPE = 2
PARAMETER C_NUM_PORTS = 2
PARAMETER C_MEM_PART_DATA_WIDTH = 16
PARAMETER C_MEM_PART_CAS_A_FMAX = 133
PARAMETER C_MEM_PART_CAS_A = 2
PARAMETER C_MEM_PART_TRAS = 60000
PARAMETER C_MEM_PART_TRASMAX = 120000000
PARAMETER C_MEM_PART_TRC = 90000
PARAMETER C_MEM_PART_CAS_B_FMAX = 143
PARAMETER C_MEM_PART_CAS_B = 2
PARAMETER C_MEM_PART_TWR = 20000
PARAMETER C_MEM_PART_TRRD = 15000
PARAMETER C_MEM_PART_TRCD = 30000
PARAMETER C_MEM_PART_TREFI = 7800000
PARAMETER C_MEM_PART_TRFC = 80000
PARAMETER C_MEM_PART_TRP = 30000
BUS_INTERFACE SPLB0 = ppc405_0_iplb1
BUS_INTERFACE SPLB1 = ppc405_0_dplb1
PORT DDR_Addr = fpga_0_DDR_SDRAM_16Mx32_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_16Mx32_DDR_BankAddr
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_16Mx32_DDR_CAS_n
PORT DDR_CE = fpga_0_DDR_SDRAM_16Mx32_DDR_CE
PORT DDR_CS_n = fpga_0_DDR_SDRAM_16Mx32_DDR_CS_n
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_16Mx32_DDR_RAS_n
PORT DDR_WE_n = fpga_0_DDR_SDRAM_16Mx32_DDR_WE_n
PORT DDR_DM = fpga_0_DDR_SDRAM_16Mx32_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_16Mx32_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_16Mx32_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_SDRAM_16Mx32_DDR_Clk
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_16Mx32_DDR_Clk_n
PORT MPMC_Clk0 = sys_clk_s
PORT MPMC_Clk90 = DDR_SDRAM_16Mx32_mpmc_clk_90_s
PORT MPMC_Clk_200MHz = clk_200mhz_s
PORT MPMC_Rst = sys_bus_reset
END