If SS is an input and is driven low
when the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware
when executing the corresponding interrupt handling vector.

Accessing IO Registers
Some registers cannot be read without affecting the state of the microprocessor. The changed state could be caused by setting or clearing status bits, or destroying the contents of the register. In this case, reading out the contents would result that further emulation of the device would be erroneous. The following registers are not directly accessible using the JTAG ICE. Grouped by AVR device.
ATmega323, and ATmega16 :
UDR, SPSR, UCSRC/UBRRH, TWCR