Вот с такими настройками прерывания идут в два раза реже, чем

Код
        T0TCR = util::bit<hw::TIMERx::timer_control::CE>::value | util::bit<hw::TIMERx::timer_control::CR>::value;
        T0CTCR = 0;
        T0PR = QQ - 1;
        T0PC = 0;
        T0MR0 = 1;
        T0MCR = util::bit<hw::TIMERx::match_control::I0>::value | util::bit<hw::TIMERx::match_control::R0>::value;
        T0CCR = 0;
        T0EMR = 0;
        T0IR = ~0;
        T0TCR = util::bit<hw::TIMERx::timer_control::CE>::value;


с таким:

Код
        T0TCR = util::bit<hw::TIMERx::timer_control::CE>::value | util::bit<hw::TIMERx::timer_control::CR>::value;
        T0CTCR = 0;
        T0PR = 0;
        T0PC = 0;
        T0MR0 = QQ;
        T0MCR = util::bit<hw::TIMERx::match_control::I0>::value | util::bit<hw::TIMERx::match_control::R0>::value;
        T0CCR = 0;
        T0EMR = 0;
        T0IR = ~0;
        T0TCR = util::bit<hw::TIMERx::timer_control::CE>::value;


Почему?

Помог вдумчивый просмотр User Manual
Fig 121. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.