#define BIT(n) (1UL<<(n))

void SpiInitHW() {
  //PIO
  PINSEL3_bit.P1_20   = 3; //SCK0
  FIO1CLR             = BIT(20); //low
  FIO1DIR_bit.P1_20   = 1; //output
  PINMODE3_bit.P1_20  = 2; //no pull-up

  PINSEL3_bit.P1_21   = 0; //PIO
  FIO1SET             = BIT(21); //high
  FIO1DIR_bit.P1_21   = 1; //output
  PINMODE3_bit.P1_21  = 2; //no pull-up

  PINSEL3_bit.P1_23   = 3; //MISO0
  FIO1DIR_bit.P1_23   = 0; //input
  PINMODE3_bit.P1_23  = 0; //pull-up (вход выведен на разъём)

  PINSEL3_bit.P1_24   = 3; //MOSI0
  FIO1CLR             = BIT(24); //low
  FIO1DIR_bit.P1_24   = 1; //output
  PINMODE3_bit.P1_24  = 2; //no pull-up

  //SPI
  PCLKSEL0_bit.PCLK_SPI = 1;
  S0SPCCR = 0x80;
  S0SPCR = BIT(5)/*MSTR*/;
}

void SpiSelect()   {FIO1CLR = BIT(21);}
void SpiDeselect() {FIO1SET = BIT(21);}

INT8U SpiTransfer(INT8U data) {
  S0SPDR = data;
  while (!S0SPSR_bit.SPIF);
  return S0SPDR;
}

//.................

  for (;;) {
    WAIT(signalSend); //ждем сигнала на передачу байта
    SpiSelect();
    SpiTransfer(mSend);
    SpiDeselect();
  }

    PCONP = (PCONP & (~PCONP_RESERV))|PCONP_PCSSP1; // Turn On EMC SSP1

    // Configure Pin Connect Block
    PINSEL0_bit.P0_7 = 0x2;           // SCK1
    PINSEL0_bit.P0_8 = 0x2;         // MISO1
    PINSEL0_bit.P0_9 = 0x2;         // MOSI1
    PINSEL0_bit.P_AT45_SSEL = 0x0;  // SSEL1 - Software Control


       FIO0SET =  (P0B_AT45_SSEL|P0B_AT45_RES|P0B_AT45_WP);     // Set Hi (Disabled)
      FIO0DIR |= (P0B_AT45_SSEL|P0B_AT45_RES|P0B_AT45_WP);    // Set ports to output

    // Warning! PClk = CClk  or 1/2 or 1/4
    SSP1CPSR = 2;        // Prescaler/2 = maximum speed
    SSP1CR0 = SSPCR0_DSS(8)|SSPCR0_SCR(1);
      
    for( int i = 0; i < SSP_FIFOSIZE; i++ )
        SSP1DR;            // Clear the RxFIFO

    // Device Enabled and selected as master
    SSP1CR1 = SSPCR1_SSE;

    PINSEL0 |= 0xC00A8000;        // CLK; MOSI1, MISO1, CLK1
    PINSEL1 |= 0x0000003C;        // MISO, MOSI;
    FIO0DIR |= (1<<CS_FPGA);        // CS_FPGA
    FIO0SET |= (1<<CS_FPGA);        // CS_FPGA
    FIO0DIR |= (1<<CS_FLASH1);        // CS_FLASH1
    FIO0SET |= (1<<CS_FLASH1);        // CS_FLASH1
    S0SPCCR = 8;    // max freq clock = 6MHz
    S0SPCR = SPI0_MSTR;
    SSP1CR0 = 0x00000007;    // max freq, clk- low defalt, second edge, spi, 8bit  
    SSP1CR1 = 0x00000002;    // SSP Enable, master
    SSP1CPSR = 4;            // max freq

    unsigned int i; unsigned int b;
    FIO0CLR |= (1<<CS_FPGA);
    S0SPDR = adr;
    while ( !(S0SPSR & SPIF) );
    i = S0SPDR;        // Flush the RxFIFO
    S0SPDR = data;
    while ( !(S0SPSR & SPIF) );
    b = (data >> 8);
    S0SPDR = b;
    while ( !(S0SPSR & SPIF) );
    FIO0SET |= (1<<CS_FPGA);
    return i;

void Flash1_ReadType(void)
{
    volatile unsigned int i;
    FIO0CLR |= (1<<CS_FLASH1);
    SSP1DR = 0x9F;
    SSP1DR = 0;
    SSP1DR = 0;
    SSP1DR = 0;
//    while ( !(SSP1SR & SSPSR_BSY) );   // SSPSR_TFE SSPSR_RNE
    i = SSP1DR;
    Flash1_ManID = SSP1DR;
    Flash1_MemType = SSP1DR;
    Flash1_MemSize = SSP1DR;
    FIO0SET |= (1<<CS_FLASH1);
}

#pragma optimize= s 9
__arm

    volatile unsigned int i;
    FIO0CLR = (1<<CS_FLASH1);
    SSP1DR = 0x9F;
    SSP1DR = 0;
    SSP1DR = 0;
    SSP1DR = 0;
    while ( !(SSP1SR & SSPSR_BSY) );
    i = SSP1DR;
    Flash1_ManID = SSP1DR;
    Flash1_MemType = SSP1DR;
    Flash1_MemSize = SSP1DR;
    FIO0SET = (1<<CS_FLASH1);

    16:         FIO0CLR = (1<<CS_FLASH1);
0x00000F78  E3A03101  MOV       R3,#__RTA_fpDbgIn(0x40000000)
0x00000F7C  E3A02040  MOV       R2,#0x00000040
0x00000F80  E2433901  SUB       R3,R3,#0x00004000
0x00000F84  E583201C  STR       R2,[R3,#0x001C]
    17:         SSP1DR = 0x9F;
0x00000F88  E3A00803  MOV       R0,#0x00030000
0x00000F8C  E3A0109F  MOV       R1,#0x0000009F
0x00000F90  E280020E  ADD       R0,R0,#WDMOD(0xE0000000)
0x00000F94  E5801008  STR       R1,[R0,#0x0008]
    18:         SSP1DR = 0;  
0x00000F98  E3A01000  MOV       R1,#Flash1_DevID(0x00000000)
0x00000F9C  E5801008  STR       R1,[R0,#0x0008]
    19:         SSP1DR = 0;  
0x00000FA0  E5801008  STR       R1,[R0,#0x0008]
    20:         SSP1DR = 0;  
0x00000FA4  E5801008  STR       R1,[R0,#0x0008]
    21:         while ( !(SSP1SR & SSPSR_BSY) );
0x00000FA8  E590100C  LDR       R1,[R0,#0x000C]
0x00000FAC  E3110010  TST       R1,#0x00000010
0x00000FB0  0AFFFFFC  BEQ       0x00000FA8
    22:         i = SSP1DR;
0x00000FB4  E5901008  LDR       R1,[R0,#0x0008]
    23:         Flash1_ManID = SSP1DR;
0x00000FB8  E590C008  LDR       R12,[R0,#0x0008]
0x00000FBC  E59F1384  LDR       R1,[PC,#0x0384]
    24:         Flash1_MemType = SSP1DR;
0x00000FC0  E581C000  STR       R12,[R1]
0x00000FC4  E590C008  LDR       R12,[R0,#0x0008]
    25:         Flash1_MemSize = SSP1DR;
0x00000FC8  E581C004  STR       R12,[R1,#0x0004]
0x00000FCC  E5900008  LDR       R0,[R0,#0x0008]
    26:         FIO0SET = (1<<CS_FLASH1);
0x00000FD0  E5810008  STR       R0,[R1,#0x0008]
0x00000FD4  E5832018  STR       R2,[R3,#0x0018]