Цитата(aaarrr @ Oct 20 2008, 19:35)

вот уж виснуть он не должен никак.
Абсолютно точно. А коль уж он виснет на этой строчке, то возможно что-то не так с SS:
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the following
actions: ....
попробуйте проинициализировать SPI и PORTB так:
Код
#define SPI_SCK PB5
#define SPI_MOSI PB4
#define SPI_MISO PB3
#define SPI_SS PB2
// initialize PORTB for SPI
DDRB |= (1 << SPI_MOSI)|(1 << SPI_SCK)|(1 << SPI_SS);
DDRB &= ~(1 << SPI_MISO);
// Enable SPI in mode 3 Master, set clock rate fck/4
SPCR = (1 << SPE)|(1 <<MSTR)|(1 << CPOL)|(1 << CPHA);
SPSR = (1 << SPI2X); // 2x rate