library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity window_2x2 is
generic ( vwidth: integer:=12 );
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w1 : out std_logic_vector(vwidth -1 downto 0);
w2 : out std_logic_vector(vwidth -1 downto 0);
w3 : out std_logic_vector(vwidth -1 downto 0)  );
end window_2x2;
architecture window of window_2x2 is
component fifo1024x12
    port (
    din: IN std_logic_VECTOR(11 downto 0);
    wr_en: IN std_logic;
    wr_clk: IN std_logic;
    rd_en: IN std_logic;
    rd_clk: IN std_logic;
    ainit: IN std_logic;
    dout: OUT std_logic_VECTOR(11 downto 0);
    full: OUT std_logic;
    empty: OUT std_logic;
    wr_count: OUT std_logic_VECTOR(9 downto 0));
end component;

component fifo4096x12
    port (
    din: IN std_logic_VECTOR(11 downto 0);
    wr_en: IN std_logic;
    wr_clk: IN std_logic;
    rd_en: IN std_logic;
    rd_clk: IN std_logic;
    ainit: IN std_logic;
    dout: OUT std_logic_VECTOR(11 downto 0);
    full: OUT std_logic;
    empty: OUT std_logic;
    wr_count: OUT std_logic_VECTOR(11 downto 0));
end component;

-- FPGA Express Black Box declaration
--attribute fpga_dont_touch: string;
--attribute fpga_dont_touch of fifo1024x14: component is "true";

-- Synplicity black box declaration
--attribute syn_black_box : boolean;
--attribute syn_black_box of fifo1024x14: component is true;
signal a1 : std_logic_vector(vwidth-1 downto 0);
signal a2 : std_logic_vector(vwidth-1 downto 0);
signal a3 : std_logic_vector(vwidth-1 downto 0);

--fifo1 signals
signal clear1 : std_logic;
signal wrreq1 : std_logic:='1';
signal rdreq1 : std_logic:='0';
signal ofull1 : std_logic;
signal oempty1 : std_logic;
signal ofifo1 : std_logic_vector(vwidth-1 downto 0);
signal ousedw1 : std_logic_vector(9 downto 0);

--fifo2 signals
signal rdreq2 : std_logic:='0';
signal ofull2 : std_logic;
signal oempty2 : std_logic;
signal ofifo2 : std_logic_vector(vwidth-1 downto 0);
signal ousedw2 : std_logic_vector(11 downto 0);


--signal ousedwa_temp: integer:=0;
--signal ousedwb_temp: integer:=0;
begin
fifo1: fifo1024x12
port map (
din => a1,
wr_en => wrreq1,
wr_clk => Clk,
rd_en => rdreq1,
rd_clk => Clk,
ainit => clear1,
dout => ofifo1,
full => ofull1,
empty => oempty1,
wr_count => ousedw1 );

fifo2: fifo4096x12
port map (
din => a2,
wr_en => wrreq1,
wr_clk => Clk,
rd_en => rdreq2,
rd_clk => Clk,
ainit => clear1,
dout => ofifo2,
full => ofull2,
empty => oempty2,
wr_count => ousedw2 );

clear1 <= not(RSTn);


clock: process(Clk,RSTn)
begin
if RSTn = '0' then
a1 <= (others=>'0');
a2 <= (others=>'0');
a3 <= (others=>'0');

w1 <= (others=>'0');
w2 <= (others=>'0');
w3 <= (others=>'0');


wrreq1 <= '0';

elsif rising_edge(Clk) then
a1 <= D;
a2 <= ofifo1;
a3 <= ofifo2;

w1 <= a1;
w2 <= a2;
w3 <= a3;

wrreq1 <= '1';

end if;
end process;

req: process(Clk)
begin
if rising_edge(Clk) then
if ousedw1 = "1111101000" then
rdreq1 <= '1';
end if;
if ousedw2 = "111110110110" then
rdreq2 <= '1';
end if;

end if;

end process;

end window;