MAC1 = (1u << 8) | (1u << 9) | (1u << 10) | (1u << 11) | (1u << 14) | (1u << 15);
        COMMAND = (1u << 3) | (1u << 4) | (1u << 5);
        OS::Sleep(1); // 250 микросекунд

        MAC1 = (1u << 1);

//---------------------------------------------------------------------------
// Initializes the EMAC Ethernet Controller
//---------------------------------------------------------------------------
int init_emac(void)
{
ulong tout;
// Select the PHY/RMII functions Pins
#if defined __IOLPC2458_H
#if EMAC_CFG_RMII // Configure I/O and the RMII / MII interface pins

// RMII or MII
tout = PINSEL2 & 0x0FC0FCF0;
PINSEL2 = tout | 0x50150105;
tout = PINSEL3 & 0x0000000F;
PINSEL3 = tout | 0x00000005;
#else
PINSEL2 = 0x55555555; // Selects P1[15:0]
tout = PINSEL3 & 0x0000000F;
PINSEL3 = tout | 0x00000005;
#endif
#endif

#if defined __IOLPC2378_H
FIO4SET |= (P4B_RES_PHY|P4B_PDOWN_PHY);
FIO4DIR |= (P4B_RES_PHY|P4B_PDOWN_PHY);

// RMII only
#if( NEW_SILICON )
tout = PINSEL2 & 0x0FC0FCF0;
PINSEL2 = tout | 0x50150105; // Selects P1[0,1,4,8,9,10,14,15]
#else
tout = PINSEL2 & 0x0FC0CCF0;
PINSEL2 = tout | 0x50151105; // Selects P1[0,1,4,6,8,9,10,14,15] (errata work-around)
#endif
tout = PINSEL3 & 0x0000000F;
PINSEL3 = tout | 0x00000005;
#endif

// Power Up the EMAC controller
PCONP |= PCONP_PCENET;
vSmartDelay_ms( 2 );

reset_emac();

if( init_phy() )
return( 1 );

install_irq( VIC_ETHERNET, (void *)eth_isr_handler, VIC_ETH_PRIOR, TRUE );

// Clear all interrupts
MINTCLEAR = ( INT_RX_OVERRUN |
INT_RX_ERROR |
INT_RX_FINISHED |
INT_RX_DONE |
INT_TX_UNDERRUN |
INT_TX_ERROR |
INT_TX_FINISHED |
INT_TX_DONE |
INT_SOFT_TRIGG |
INT_WAKEUP );


// Enable EMAC interrupts
MINTENABLE = ( INT_RX_OVERRUN |
INT_RX_DONE |
INT_TX_UNDERRUN |
INT_TX_ERROR |
INT_TX_DONE );


// Enable receive and transmit mode of MAC Ethernet core
MCOMMAND |= (CR_RX_ENABLE|CR_TX_ENABLE);
MAC1 = (MAC1 & MAC1_MASK)|MAC1_RX_ENABLE;

return( 0 );
}
//---------------------------------------------------------------------------
// Resets the chip and leaves it in an idle state
//---------------------------------------------------------------------------
int reset_emac(void)
{
// Reset all EMAC internal modules.
MAC1 = MAC1_RES_TX|MAC1_RES_MCS_TX|MAC1_RES_RX|MAC1_RES_MCS_RX|
MAC1_SIM_RESET|MAC1_SOFT_RESET;
// Reset all datapaths and the host registers
MCOMMAND = CR_REG_RESET|CR_TX_RESET|CR_RX_RESET;

MAC2 = MAC2_CRC_ENABLE|MAC2_PAD_ENABLE|MAC2_ADET_PAD_ENABLE;

IPGT = IPGT_HALF_DUPLEX;
IPGR = IPGR_DEF; // Collission Windows Retry register (default value)
CLRT = CLRT_DEF; // Set the Non Back to Back Inter Pkt Gap to recm'd value
MAXF = ETH_MAX_FLEN; // Accept maximum sized frames
// Set the Ethernet MAC Address registers
SA2 = mymac.sa2;
SA1 = mymac.sa1;
SA0 = mymac.sa0;

MAC1 = 0; // Deassert all prior resets
// Initialize Tx and Rx DMA Descriptors
rx_descr_init();
tx_descr_init();

RXFILTERCTRL = RFC_BCAST_EN|RFC_PERFECT_EN; // Accept Broadcast and Perfect Address frames
return( 0 );
}

    MAC_and_PHY_power(true);
    configure_pins_as_GPIO();
    set_strapin_values(settings);
    __no_operation();
    __no_operation();
    __no_operation();
    __no_operation();
    hw::GPIO::eth_PHY::start(true);
    OS::Sleep(1 + util::microseconds2ttimeout(pcb::Ethernet_PHY_startup_time_mcs));
    
    configure_pins_as_ethernet();

    MAC1 =
        util::bit<MAC1_reset_tx>::value |
        util::bit<MAC1_reset_mcs_tx>::value |
        util::bit<MAC1_reset_rx>::value |
        util::bit<MAC1_reset_mcs_rx>::value |
        util::bit<MAC1_simulation_reset>::value |
        util::bit<MAC1_soft_reset>::value;
    __no_operation();
    
    COMMAND =
        /*util::bit<COMMAND_tx_reset>::value |
        util::bit<COMMAND_rx_reset>::value |
        util::bit<COMMAND_reg_reset>::value |*/
        util::bit<COMMAND_RMII>::value;
    __no_operation();
    
    MAC2 =
        util::bit<MAC2_frame_length_checking>::value |
        util::bit<MAC2_crc_enable>::value |
        util::bit<MAC2_pad_crc_enable>::value |
        util::bit<MAC2_auto_detect_pad_enable>::value;
    __no_operation();