Timing constraint: TIMEGRP "ADC_DATA_port" OFFSET = IN 0.6 ns BEFORE COMP "FPGA_CLK2_p";

24 items analyzed, 12 timing errors detected. (12 setup errors, 0 hold errors)
Minimum allowable offset is 2.240ns.
--------------------------------------------------------------------------------
Slack: -1.640ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: ADC_D_p[9] (PAD)
Destination: AdcModule_INST/reg_adc_data1(9) (FF)
Destination Clock: fpga_clk1 rising at 0.000ns
Requirement: 0.600ns
Data Path Delay: 6.930ns (Levels of Logic = 2)
Clock Path Delay: 4.690ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: ADC_D_p[9] to AdcModule_INST/reg_adc_data1(9)

Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.255 ADC_D_p[9]
AdcModule_INST/adc_d_ibufs_9_adc_d_ibuf/IBUFDS
net (fanout=1) 0.099 AdcModule_INST/adc_d[9]
Tidockd 5.576 AdcModule_INST/adc_data1[9].DELAYCHAIN
AdcModule_INST/reg_adc_data1(9)
---------------------------- ---------------------------
Total 6.930ns (6.831ns logic, 0.099ns route)
(98.6% logic, 1.4% route)

Clock Path: FPGA_CLK2_p to AdcModule_INST/reg_adc_data1(9)
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.013 FPGA_CLK2_p
fpga_clk2_ibufg/IBUFDS
net (fanout=2) 0.672 fpga_clk1_buf
Tbgcko_O 0.708 fpga_clk1_inst
net (fanout=118) 2.297 fpga_clk1
---------------------------- ---------------------------
Total 4.690ns (1.721ns logic, 2.969ns route)
(36.7% logic, 63.3% route)

Tidockd 5.576 AdcModule_INST/adc_data1[9].DELAYCHAIN
AdcModule_INST/reg_adc_data1(9)