module kip (
            input clk,
            input sin,
            input cos,
            input zap,
            input [2:0] cs,
            output [7:0] Q  
            );
wire WIRE_PLUS, WIRE_MINUS;

detector det ( .clk(clk),
               .sin(sin),
               .cos(cos),
               .plus(WIRE_PLUS),
               .minus(WIRE_MINUS)
              );

count24 co24 ( .UP(WIRE_PLUS),
               .DW(WIRE_MINUS),
               .zap(zap),
               .cs(cs),
               .Q(Q)
               );
endmodule
//********************************************************************************

module detector(input clk,
                input sin,        
                input cos,        
                output plus,    
                output minus  
                );
wire WIRE_1, WIRE_2, WIRE_3, WIRE_4;
wire WIRE_XOR_1, WIRE_XOR_2;

always @ (posedge clk)
begin
    WIRE_2 = WIRE_1;
    WIRE_1 = sin;
    WIRE_4 = WIRE_3;
    WIRE_3 = cos;
    WIRE_XOR_1 = WIRE_1 ^ WIRE_4;
    WIRE_XOR_2 = WIRE_2 ^ WIRE_3;
    plus = ~WIRE_XOR_1 & WIRE_XOR_2;
    minus = ~WIRE_XOR_2 & WIRE_XOR_1;
end

endmodule                
//********************************************************************************

module count24 (
                input UP,DW,
                input zap,              
                input [2:0] cs,        
                output [7:0] Q        
                );

wire ck;
wire [23:0] counter, buffer;

assign ck = UP | DW;

always @ (posedge ck)
begin
    if(UP)
     counter <= counter+1;
    else if(DW)
     counter <= counter-1;
end  

always @ (posedge zap)
begin
buffer <= counter;
end

assign Q[7:0] = (cs == 3'b001) ? buffer[7:0]:7'bZ;     //Передача младших 8разрядов буффера на выход
assign Q[7:0] = (cs == 3'b010) ? buffer[15:8]:7'bZ;   //Передача средних 8разрядов буфф. на выход
assign Q[7:0] = (cs == 3'b100) ? buffer[23:16]:7'bZ; //Передача старших 8разр. буфф. на вых.

endmodule