module div(num, den, quot, rem, m16, divz, sn, sd, frct, n_in, n_out, cycle, clock);

input  [15:0] num; // numerator
input [15:0] den; // denominator
output [15:0] quot; // quotient
output [15:0] rem; // remainder
output divz, n_out; // divide-by-zero & sign bits
input m16, sn, sd, frct, n_in, cycle, clock; // 8/16_mode, numerator_signed, denominator_signed, fractional/normal, sign_from_PSW, cpu_cycle_#, clock

wire [15:0] int_den, int_num, int_quot, ext_num, ext_den, int_rem;

wire nsgn, dsgn, qsgn;
assign nsgn = sn & (m16 ? num[15] : num[7]);
assign dsgn = sd & (m16 ? den[15] : den[7]);
assign qsgn = nsgn ^ dsgn;

assign ext_num = m16 ? num : { {8{nsgn}}, num[7:0]};
assign ext_den = m16 ? den : { {8{dsgn}}, den[7:0]};

assign int_num = (ext_num ^ {16{nsgn}}) + nsgn;
assign int_den = (ext_den ^ {16{dsgn}}) + dsgn;

assign divz = !(|int_den);

wire en_frct = frct & (int_num < int_den); // fractional mode only if |num| < |den|
wire numz = !(|int_num);

reg [3:0] i;
reg [16:0] temp;
reg [15:0] save_rem;
reg [17:0] temp1;
reg [7:0] out, save_out;

always @*
begin
  temp = cycle ? {save_rem, int_num[7] & !(en_frct)} :
           (en_frct ? {int_num, 1'b0} : {16'h0000,int_num[m16?15:7]});
  for (i=0; i<8; i = i+1'b1)
    begin
      temp1 = temp - int_den;
      out[7-i] = !temp1[17];
      if (i != 7) temp = {(temp1[17] ? temp[15:0] : temp1[15:0]), int_num[(cycle | !m16) ? (6-i) : (14-i)] & !(en_frct)};
        else temp = {1'b0, (temp1[17] ? temp[15:0] : temp1[15:0])};
    end
end
  
always @(posedge clock)
  if (!cycle) save_rem <= temp[15:0];

always @(posedge clock)
  if (!cycle) save_out <= out;

assign int_quot = {save_out, out};
assign int_rem = temp[15:0];

// sign of remaider :
// sign of remainder is equal to sign of numerator.
assign rem = (int_rem ^ {16{nsgn}}) + nsgn;  

// sign of quotient :
// fractional mode - quotient always positive
// integer mode - quotient has sign of den*num
wire t_qsgn = qsgn & !frct;
assign quot = (int_quot ^ {16{t_qsgn}}) + t_qsgn;

// sign output:
// fractional mode - if numerator not zero, put sign into N
// integer mode - put sign into N
assign n_out = (!numz | !frct) ? qsgn : n_in;

endmodule

    imm    0xFF00
    lea    r5,0x0

risc_st.rar\risc_st\risc_st_core\compile\risc_cpu.vhd
risc_st.rar\risc_st\risc_st_core\compile\risc_st_core.vhd
risc_st.rar\risc_st\risc_st_core\compile\risc_sync.vhd