library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

entity clk_gen is
    port(
        ena            : in STD_LOGIC;
        clk            : out STD_LOGIC
        );
end clk_gen;

architecture a of clk_gen is
    COMPONENT LCELL
        PORT (a_in : IN STD_LOGIC;
            a_out : OUT STD_LOGIC);
    END COMPONENT;

    signal out_reg : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');

begin

    out_reg(0) <= ena and out_reg(3);

    LCELL1 : LCELL
        PORT MAP(
            a_in => out_reg(0),
            a_out=> out_reg(1)
            );
    
    LCELL2 : LCELL
        PORT MAP(
            a_in => out_reg(1),
            a_out=> out_reg(2)
            );
    
    out_reg(3) <= not(out_reg(2));

    clk <= out_reg(2);
end a;