/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
  required, then adjust the Register Addresses */

  /*!< Enable FSMC clock */
  RCC->AHBENR = 0x00000114;

  /*!< Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
  RCC->APB2ENR = 0x000001E0;

/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
/*----------------  SRAM Address lines configuration -------------------------*/
/*----------------  NOE and NWE configuration --------------------------------*/
/*----------------  NE3 configuration ----------------------------------------*/
/*----------------  NBL0, NBL1 configuration ---------------------------------*/

  GPIOD->CRL = 0x44BB44BB;
  GPIOD->CRH = 0xBBBBBBBB;

  GPIOE->CRL = 0xB44444BB;
  GPIOE->CRH = 0xBBBBBBBB;

  GPIOF->CRL = 0x44BBBBBB;
  GPIOF->CRH = 0xBBBB4444;

  GPIOG->CRL = 0x44BBBBBB;
  GPIOG->CRH = 0x44444B44;

/*----------------  FSMC Configuration ---------------------------------------*/
/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/

  FSMC_Bank1->BTCR[4] = 0x00001011;
  FSMC_Bank1->BTCR[5] = 0x00000200;

....
define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__] |
                             mem:[from __ICFEDIT_region_SRAM_start__   to __ICFEDIT_region_SRAM_end__];
...
place in RAM_region   { readwrite,
                        block CSTACK,
                        block HEAP };

...
__root __no_init uint8_t buf1[6550];

__root __no_init uint8_t buf[65500];
...

  uint8_t *ptr = &buf[0];
  for(uint_fast32_t i = 0; i < 256; i++)
  {
     *ptr++ = i;
  }

  ptr = &buf[0];
  for(uint_fast32_t i = 0; i < 256; i++)
  {
    if( *ptr++ != i )
    {
       GPIO_SetBits(GPIOF, GPIO_Pin_9);
       GPIO_SetBits(GPIOF, GPIO_Pin_6);
       while(1);
    }
  }