cstartup.s
In function: Assembler
Diagnostic: non-initialized parameter
Line: 271   P0: 0    P1: 0

        MODULE  ?cstartup
...
        END

MODULE ?cstartup

T1IR EQU 0xE0008000

FIO0PIN EQU 0x3FFFC014
FIO0SET EQU 0x3FFFC018
FIO0CLR EQU 0x3FFFC01C
FIO1PIN EQU 0x3FFFC034
FIO1SET EQU 0x3FFFC038
FIO1CLR EQU 0x3FFFC03C


;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)

SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector
PUBLIC __vector_0x14
CODE32 ; Always ARM mode after reset

__vector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.

__program_start:
ldr pc,=?cstartup ; Absolute jump can reach 4 GByte
b __program_start
b __program_start
b __program_start
b __program_start
__vector_0x14:
DCD 0xa55f8de3 ; CheckSum - трэба рассчитать в Phillips Utility
ldr pc,[PC,#-0xFF0]
; ldr pc,=fiq_handler ; вектор FIQ

; вместо перехода на FIQ, обработчик FIQ стоит прямо здесь, то есть переход не нужен

MVN R8,#~0x3FFFFFC0
...
SUBS PC,LR,#4 ; стандартный возврат из FIQ

LTORG


; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reser execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;
SECTION .text:CODE:NOROOT(2)
PUBLIC __iar_program_start
EXTERN ?main
REQUIRE __vector
CODE32

__iar_program_start:
?cstartup:

;
; Add initialization needed before setup of stackpointers here.
;

;
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
;


; --------------------
; Mode, correspords to bits 0-5 in CPSR

MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR

USR_MODE DEFINE 0x10 ; User mode
FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
SVC_MODE DEFINE 0x13 ; Supervisor mode
ABT_MODE DEFINE 0x17 ; Abort mode
UND_MODE DEFINE 0x1B ; Undefined Instruction mode
SYS_MODE DEFINE 0x1F ; System mode


MRS r0, cpsr ; Original PSR value

; ;; Set up the SVC stack pointer.
; MSR cpsr_c, r0 ; Change the mode
; LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK

;; Set up the interrupt stack pointer.

BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK

; ;; Set up the fast interrupt stack pointer.
;
; BIC r0, r0, #MODE_MSK ; Clear the mode bits
; ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
; MSR cpsr_c, r0 ; Change the mode
; LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
;
; ;; Set up the ABT stack pointer.
; BIC r0, r0, #MODE_MSK ; Clear the mode bits
; ORR r0, r0, #ABT_MODE ; Set abort mode bits
; MSR cpsr_c, r0 ; Change the mode
; LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
;
; ;; Set up the UND stack pointer.
; BIC r0, r0, #MODE_MSK ; Clear the mode bits
; ORR r0, r0, #UND_MODE ; Set UND mode bits
; MSR cpsr_c, r0 ; Change the mode
; LDR sp, =SFE(UND_STACK) ; End of UND_STACK

;; Set up the normal stack pointer.

BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
ORR r0 ,r0, #SYS_MODE ; Set System mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(CSTACK) ; End of CSTACK

#ifdef __ARMVFP__
;; Enable the VFP coprocessor.

MOV r0, #0x40000000 ; Set EN bit in VFP
FMXR fpexc, r0 ; FPEXC, clear others.

;
; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
;

MOV r0, #0x01000000 ; Set FZ bit in VFP
FMXR fpscr, r0 ; FPSCR, clear others.
#endif

;
; Add more initialization here
;

; Continue to ?main for C-level initialization.

LDR r0, =?main
BX r0


SECTION .text:CODE:NOROOT(2)
PUBLIC READADCBUF
EXTERN buf ; u8 buf[3800]
CODE32

READADCBUF: STMDB SP!,{R0-R5} ; вызывается где-то из проги
LDR R0,=buf+0
LDR R1,=buf+1900
MVN R2,#~0x3FFFFFC0
BIC R2,R2,#0x3FC0
...
ReadAdcBuf_NOP:
REPT 60
NOP
ENDR
B ReadAdcBuf_NOP
ReadAdcBuf_NOP_END:

LTORG

END