void initUart1(tU16 div_factor, tU8 mode, tU8 fifo_mode)
{
  volatile tU32 dummy;
  
  //UART1 power/clock control bit.
  //Power: In the PCONP register (Table 4–63), set bits PCUART1.
  //Remark: On reset, UART1 is enabled (PCUART1 = 1).
  PCONP |= 1<<4;

  //Peripheral clock: In the PCLK_SEL0 register (Table 4–56), select PCLK_UART1.
  //9:8 PCLK_UART1 Peripheral clock selection for UART1.
  PCLKSEL0 |= (1<<8)|(1<<9);

  //enable uart #1 pins in GPIO (P3.16 = TxD1, P3.17 = RxD1)
  PINSEL7 = (PINSEL7 & 0xfffffff0) | 0x0000000F;

  U1IER = 0x00;                        //disable all uart interrupts
  dummy = U1IIR;                       //clear all pending interrupts
  dummy = U1RBR;                       //clear receive register
  dummy = U1LSR;                       //clear line status register

  //Baud rate: In register U1LCR (Table 17–405), set bit DLAB =1. This enables access
  //to registers DLL (Table 17–399) and DLM (Table 17–400) for setting the baud rate.
  //Also, if needed, set the fractional baud rate in the fractional divider register
  //(Table 17–412).
  //set the bit rate = set uart clock (pclk) divisionfactor
  U1LCR = 0x80;                        //enable divisor latches (DLAB bit set, bit 7)
  U1DLL = (tU8)div_factor;             //write division factor LSB
  U1DLM = (tU8)(div_factor >> 8);      //write division factor MSB

  //set transmissiion and fifo mode
  U1LCR = (mode & ~0x80);              //DLAB bit (bit 7) must be reset

  //UART FIFO: Use bit FIFO enable (bit 0) in register U0FCR (Table 17–404) to enable FIFO.
  U1FCR = fifo_mode;

  //initialize the interrupt vector
  VICIntSelect &= ~0x00000080;      // UART1 selected as IRQ
  VICVectCntl7  =  0x00000027;
  VICVectAddr7  =  (tU32)uart1ISR;  // address of the ISR
  VICIntEnable |=  0x00000080;      // UART1 interrupt enabled

  //Interrupts: To enable UART interrupts set bit DLAB =0 in register U1LCR
  //(Table 17–405). This enables access to U1IER (Table 17–401). Interrupts are enabled
  //in the VIC using the VICIntEnable register (Table 7–106).
  //enable receiver interrupts
  //U1IER = 0x01;
  U1IER = 0x03;
}