DCM_BASE #(
              .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
              // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
              .CLKFX_DIVIDE(2), // Can be any integer from 1 to 32
              .CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32
              .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
              .CLKIN_PERIOD(28.4), // Specify period of input clock in ns from 1.25 to 1000.00
              .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
              .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
              .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
              .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
              // an integer from 0 to 15
              .DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis
              .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
              .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
              .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
              .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
              .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
              ) DCM_SDRAM_inst(
                              .CLK0(sdr_clk), // 0 degree DCM CLK output
                              .CLK90(sdr90_clk), //
                              //.CLKFB(sdrclkfb), // DCM clock feedback
                                        .CLKFB(sdrclk),
                              .CLKIN(bus_clk), // Clock input (from IBUFG, BUFG or DCM)
                              .RST(bus_reset) // DCM asynchronous reset input
                              );

   ////CLOCK