INCLUDE "lpm_decode.inc";

SUBDESIGN ssi
(
out[108..01] :BIDIR;
D[7..0] :BIDIR;
A[7..0] :INPUT;
nRD :INPUT;
nWR :INPUT;
nCS :INPUT;
-- ALE :INPUT;
)

Variable
decmem0 : lpm_decode WITH (LPM_WIDTH=4, LPM_DECODES=14,LPM_PIPELINE=0);
reg_out[13..00][07..00] : DFFE; -- addresses 0..13
reg_oute[13..00][07..00] : DFFE; -- addresses 16..39
dtri[07..00] : TRI;
outtri[13..00][07..00] : TRI;
BEGIN
decmem0.data[] = a[3..0];
decmem0.enable = !nCS;

reg_out[][].prn = vcc;
reg_out[][].clrn = vcc;
reg_out[][].d = D[];
reg_out[][].clk = nWR;

reg_oute[][].prn = vcc;
reg_oute[][].clrn = vcc;
reg_oute[][].d = D[];
reg_oute[][].clk = nWR;

-- generation of input structure
for i in 0 to 13 generate
reg_out[i][].ena = decmem0.eq[i] & !nCS & !a[4];
reg_oute[i][].ena = decmem0.eq[i] & !nCS & a[4];
end generate;
-- generation of output structure
for i in 0 to 12 generate
outtri[i][].oe = reg_oute[i][].q;
outtri[i][].in = VCC; --reg_out[i][].q;
out[i*8+8..i*8+1] = outtri[i][].out;
end generate;
outtri[13][3..0].in = reg_out[13][3..0].q;
out[108..105] = outtri[13][3..0].out;
END;

module tri_oe
(
input clk,
input [7:0] data,
input ena,
input [3:0] sel,
output [111:0] out
);


reg [7:0] rg_dffe [13:0];

wire [111:0] rg;

integer i;
always @(posedge clk)
begin
for (i=0; i<=13 ; i=i+1)
if ((sel == i) && ena) rg_dffe[i] <= data;
end

genvar j;
generate for(j=0; j<=13; j=j+1)
begin:block
assign rg[j*8+7:j*8] = rg_dffe[j];
end
endgenerate

genvar l;
generate for(l=0; l<=111; l=l+1)
begin:tri_oe
assign out[l] = rg[l] ? 1'b0 : 1'bz;
end
endgenerate

endmodule