/* PC3 (TXD0) as output. */
PORTC_OUTSET |= (1<<3) | (1<<2);
PORTC_DIRSET |= 1<<3;

/*  9600 */
USARTC0_BAUDCTRLA = 195;//0x03;
USARTC0_BAUDCTRLB = 0;//(9 << USART_BSCALE0_bp )  | (0x06);

/* USARTC0, 8 Data bits, No Parity, 1 Stop bit. */
USARTC0_CTRLC = 3;

/*  USART_Tx_Enable */
USARTC0_CTRLB = USART_TXEN_bm;

        DMA.CTRL = DMA_ENABLE_bm; // Enable DMA
    DMA.CH0.ADDRCTRL =     DMA_CH_SRCRELOAD_NONE_gc     |
                        DMA_CH_SRCDIR_INC_gc         |
                        DMA_CH_DESTRELOAD_NONE_gc     |
                        DMA_CH_DESTDIR_FIXED_gc;
    

    DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_USARTC0_DRE_gc;
    DMA.CH0.TRFCNT = sizeof(str_5);
    //DMA.CH0.REPCNT = 1;

    DMA.CH0.SRCADDR0 = (( (uint32_t) str_5) >> 0*8 ) & 0xFF;
    DMA.CH0.SRCADDR1 = (( (uint32_t) str_5) >> 1*8 ) & 0xFF;
    DMA.CH0.SRCADDR2 = (( (uint32_t) str_5) >> 2*8 ) & 0xFF;

    DMA.CH0.DESTADDR0 = (( (uint32_t) (&USARTC0_DATA)) >> 0*8 ) & 0xFF;
    DMA.CH0.DESTADDR1 = (( (uint32_t) (&USARTC0_DATA)) >> 1*8 ) & 0xFF;
    DMA.CH0.DESTADDR2 = (( (uint32_t) (&USARTC0_DATA)) >> 2*8 ) & 0xFF;
    
    DMA.CH0.CTRLA = DMA_CH_BURSTLEN_8BYTE_gc;
    
    DMA.CH0.CTRLA |= DMA_CH_ENABLE_bm;
    DMA.CH0.CTRLA |=  DMA_CH_TRFREQ_bm;

    while( !(DMA.CH0.CTRLB & (DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm)) );

        DMA.CTRL = DMA_ENABLE_bm; // Enable DMA
    DMA.CH0.ADDRCTRL =     DMA_CH_SRCRELOAD_NONE_gc     |
                        DMA_CH_SRCDIR_INC_gc                 |
                        DMA_CH_DESTRELOAD_NONE_gc     |
                        DMA_CH_DESTDIR_FIXED_gc;
    

    DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_USARTC0_DRE_gc;
    DMA.CH0.TRFCNT = sizeof(str_5);

    DMA.CH0.SRCADDR0 = (( (uint32_t) str_5) >> 0*8 ) & 0xFF;
    DMA.CH0.SRCADDR1 = (( (uint32_t) str_5) >> 1*8 ) & 0xFF;
    DMA.CH0.SRCADDR2 = (( (uint32_t) str_5) >> 2*8 ) & 0xFF;

    DMA.CH0.DESTADDR0 = (( (uint32_t) (&USARTC0_DATA)) >> 0*8 ) & 0xFF;
    DMA.CH0.DESTADDR1 = (( (uint32_t) (&USARTC0_DATA)) >> 1*8 ) & 0xFF;
    DMA.CH0.DESTADDR2 = (( (uint32_t) (&USARTC0_DATA)) >> 2*8 ) & 0xFF;
    
    DMA.CH0.CTRLA = DMA_CH_SINGLE_bm;
    
    DMA.CH0.CTRLA |= DMA_CH_ENABLE_bm;

    while( !(DMA.CH0.CTRLB & (DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm)) );