00000000: 1000001d beq $0,$0,0x78
00000004: 00000000 nop
00000008: 00000000 nop
0000000c: 00000000 nop
00000010: 00000000 nop
00000014: 00000000 nop
00000018: 00000000 nop
0000001c: 00000000 nop
00000020: 41503532 cop0 0x1503532
00000024: 2d415232 sltiu $1,$10,21042=0x5232
00000028: 3331362d andi $17,$25,0x362d
0000002c: 52542020 beql $18,$20,0x80b0
00000030: 20202020 addi $0,$1,8224=0x2020
00000034: 202d3030 addi $13,$1,12336=0x3030
00000038: 30302e30 andi $16,$1,0x2e30
0000003c: 302e3030 andi $14,$1,0x3030
00000040: 00112233 tltu $0,$17,0x088
00000044: 44550000 cop1 0x0550000
00000048: 5468752c bnel $3,$8,0x1d4fc
0000004c: 20313420 addi $17,$1,13344=0x3420
00000050: 41707220 cop0 0x1707220
00000054: 32303035 andi $16,$17,0x3035
00000058: 20202020 addi $0,$1,8224=0x2020
0000005c: 41503532 cop0 0x1503532
00000060: 20426f6f addi $2,$2,28527=0x6f6f
00000064: 74726f6d const 0x74726f6d
00000068: 20202020 addi $0,$1,8224=0x2020
0000006c: 20202020 addi $0,$1,8224=0x2020
00000070: 00010003 sra $0,$1,0
00000074: 00000006 srlv $0,$0,$0
00000078: 3c08b100 lui $8,0xb100
0000007c: 35080050 ori $8,$8,0x50
00000080: 24090001 addiu $9,$0,1
00000084: ad090000 sw $9,0($8)
00000088: 00000000 nop
0000008c: 3c04b100 lui $4,0xb100
00000090: 34840064 ori $4,$4,0x64
00000094: 8c880000 lw $8,0($4)
00000098: 2401fffc addiu $1,$0,-4=0xfffc
0000009c: 01014024 and $8,$8,$1
000000a0: 35080003 ori $8,$8,0x3
000000a4: 2401ff83 addiu $1,$0,-125=0xff83
000000a8: 01014024 and $8,$8,$1
000000ac: 3508005c ori $8,$8,0x5c
000000b0: 2401ff7f addiu $1,$0,-129=0xff7f
000000b4: 01014024 and $8,$8,$1
000000b8: 35080000 ori $8,$8,0x0
000000bc: 3c01fffe lui $1,0xfffe
000000c0: 34213fff ori $1,$1,0x3fff
000000c4: 01014024 and $8,$8,$1
000000c8: 35080000 ori $8,$8,0x0
000000cc: 3c01ff8f lui $1,0xff8f
000000d0: 3421ffff ori $1,$1,0xffff
000000d4: 01014024 and $8,$8,$1
000000d8: 35080000 ori $8,$8,0x0
000000dc: ac880000 sw $8,0($4)
000000e0: 0000000f sync 0
000000e4: 00000000 nop
000000e8: 00000000 nop
000000ec: 00000000 nop
000000f0: 00000000 nop
000000f4: 3c04b100 lui $4,0xb100
000000f8: 3484006c ori $4,$4,0x6c
000000fc: 8c880000 lw $8,0($4)
00000100: 2401fffc addiu $1,$0,-4=0xfffc
00000104: 01014024 and $8,$8,$1
00000108: 35080000 ori $8,$8,0x0
0000010c: 2401fff3 addiu $1,$0,-13=0xfff3
00000110: 01014024 and $8,$8,$1
00000114: 35080000 ori $8,$8,0x0
00000118: ac880000 sw $8,0($4)
0000011c: 0000000f sync 0
00000120: 00000000 nop
00000124: 00000000 nop
00000128: 00000000 nop
0000012c: 00000000 nop
00000130: 3c04b100 lui $4,0xb100
00000134: 34840070 ori $4,$4,0x70
00000138: 8c880000 lw $8,0($4)
0000013c: 2401fffc addiu $1,$0,-4=0xfffc
00000140: 01014024 and $8,$8,$1
00000144: 35080000 ori $8,$8,0x0
00000148: 2401fff3 addiu $1,$0,-13=0xfff3
0000014c: 01014024 and $8,$8,$1
00000150: 35080004 ori $8,$8,0x4
00000154: ac880000 sw $8,0($4)
00000158: 0000000f sync 0
0000015c: 3c04b100 lui $4,0xb100
00000160: 348400b4 ori $4,$4,0xb4
00000164: 24080000 addiu $8,$0,0
00000168: ac880000 sw $8,0($4)
0000016c: 0000000f sync 0
00000170: 00000000 nop
00000174: 00000000 nop
00000178: 00000000 nop
0000017c: 00000000 nop
00000180: 40806800 mtc0 $0,R13
00000184: 00000000 nop
00000188: 3c081040 lui $8,0x1040
0000018c: 40886000 mtc0 $8,R12
00000190: 00000000 nop
00000194: 00000000 nop
00000198: 00000000 nop
0000019c: 40809000 mtc0 $0,R18
000001a0: 00000000 nop
000001a4: 40809800 mtc0 $0,R19
000001a8: 00000000 nop
000001ac: 3c04b100 lui $4,0xb100
000001b0: 34840018 ori $4,$4,0x18
000001b4: 24080000 addiu $8,$0,0
000001b8: ac880000 sw $8,0($4)
000001bc: 00000000 nop
000001c0: 3c04b100 lui $4,0xb100
000001c4: 34840050 ori $4,$4,0x50
000001c8: 24080001 addiu $8,$0,1
000001cc: ac880000 sw $8,0($4)
000001d0: 24080001 addiu $8,$0,1
000001d4: 00000000 nop
000001d8: 40884800 mtc0 $8,R9
000001dc: 00000000 nop
000001e0: 40805800 mtc0 $0,R11
000001e4: 00000000 nop
000001e8: 3c084000 lui $8,0x4000
000001ec: 35080ff8 ori $8,$8,0xff8
000001f0: 40889800 mtc0 $8,R19
000001f4: 00000000 nop
000001f8: 24080007 addiu $8,$0,7
000001fc: 40889000 mtc0 $8,R18
00000200: 00000000 nop
00000204: 3c04b100 lui $4,0xb100
00000208: 3484003c ori $4,$4,0x3c
0000020c: 3c06b100 lui $6,0xb100
00000210: 34c600a8 ori $6,$6,0xa8
00000214: 8cc90000 lw $9,0($6)
00000218: 3c0a0555 lui $10,0x555
0000021c: 354a1212 ori $10,$10,0x1212
00000220: 152a0001 bne $9,$10,0x228
00000224: 10000009 beq $0,$0,0x24c
00000228: 3c05b100 lui $5,0xb100
0000022c: 34a50038 ori $5,$5,0x38
00000230: 24080004 addiu $8,$0,4
00000234: 3c0936d6 lui $9,0x36d6
00000238: 35291600 ori $9,$9,0x1600
0000023c: aca90000 sw $9,0($5)
00000240: 0000000f sync 0
00000244: ac880000 sw $8,0($4)
00000248: 0000000f sync 0
0000024c: 04110019 bgezal $0,0x2b4
00000250: 00000000 nop
00000254: 04110025 bgezal $0,0x2ec
00000258: 00000000 nop
0000025c: 04110045 bgezal $0,0x374
00000260: 00000000 nop
00000264: 40088000 mfc0 $8,R16
00000268: 00000000 nop
0000026c: 31090380 andi $9,$8,0x380
00000270: 2129ff80 addi $9,$9,-128=0xff80
00000274: 11200006 beq $9,$0,0x290
00000278: 00000000 nop
0000027c: 3c0181ff lui $1,0x81ff
00000280: 3421ffff ori $1,$1,0xffff
00000284: 01014024 and $8,$8,$1
00000288: 3c012400 lui $1,0x2400
0000028c: 01014025 or $8,$8,$1
00000290: 2401fff8 addiu $1,$0,-8=0xfff8
00000294: 01014024 and $8,$8,$1
00000298: 40888000 mtc0 $8,R16
0000029c: 00000000 nop
000002a0: 00000000 nop
000002a4: 0411004a bgezal $0,0x3d0
000002a8: 00000000 nop
000002ac: 0411007f bgezal $0,0x4ac
000002b0: 00000000 nop
000002b4: 3c04b130 lui $4,0xb130
000002b8: 8c880000 lw $8,0($4)
000002bc: 3c01fcff lui $1,0xfcff
000002c0: 3421ffff ori $1,$1,0xffff
000002c4: 01014024 and $8,$8,$1
000002c8: 3c010100 lui $1,0x100
000002cc: 01014025 or $8,$8,$1
000002d0: ac880000 sw $8,0($4)
000002d4: 0000000f sync 0
000002d8: 00000000 nop
000002dc: 00000000 nop
000002e0: 00000000 nop
000002e4: 03e00008 jr $31
000002e8: 00000000 nop
000002ec: 3c06b030 lui $6,0xb030
000002f0: 8cc80000 lw $8,0($6)
000002f4: 24018007 addiu $1,$0,-32761=0x8007
000002f8: 01014024 and $8,$8,$1
000002fc: 24090000 addiu $9,$0,0
00000300: 35290e00 ori $9,$9,0xe00
00000304: 35290160 ori $9,$9,0x160
00000308: 35290008 ori $9,$9,0x8
0000030c: 01094025 or $8,$8,$9
00000310: acc80000 sw $8,0($6)
00000314: 0000000f sync 0
00000318: 3c06b030 lui $6,0xb030
0000031c: 34c60010 ori $6,$6,0x10
00000320: 2408059f addiu $8,$0,1439=0x059f
00000324: acc80000 sw $8,0($6)
00000328: 0000000f sync 0
0000032c: 3c06b030 lui $6,0xb030
00000330: 34c60004 ori $6,$6,0x4
00000334: 8cc80000 lw $8,0($6)
00000338: 2401fffc addiu $1,$0,-4=0xfffc
0000033c: 01014024 and $8,$8,$1
00000340: 35080001 ori $8,$8,0x1
00000344: acc80000 sw $8,0($6)
00000348: 0000000f sync 0
0000034c: 3c06b030 lui $6,0xb030
00000350: 34c6000c ori $6,$6,0xc
00000354: 24083089 addiu $8,$0,12425=0x3089
00000358: acc80000 sw $8,0($6)
0000035c: 0000000f sync 0
00000360: 8cc80000 lw $8,0($6)
00000364: 31090001 andi $9,$8,0x1
00000368: 1520fffd bne $9,$0,0x360
0000036c: 03e00008 jr $31
00000370: 00000000 nop
00000374: 40088001 mfc0 $8,R16.1
00000378: 3c017e00 lui $1,0x7e00
0000037c: 01014024 and $8,$8,$1
00000380: 00084642 srl $8,$8,25
00000384: 11000010 beq $8,$0,0x3c8
00000388: 40801000 mtc0 $0,R2
0000038c: 00000000 nop
00000390: 40801800 mtc0 $0,R3
00000394: 00000000 nop
00000398: 24092000 addiu $9,$0,8192=0x2000
0000039c: 40802800 mtc0 $0,R5
000003a0: 00000000 nop
000003a4: 40895000 mtc0 $9,R10
000003a8: 00000000 nop
000003ac: 40880000 mtc0 $8,R0
000003b0: 00000000 nop
000003b4: 42000002 cop0 0x2000002
000003b8: 2108ffff addi $8,$8,-1=0xffff
000003bc: 21292000 addi $9,$9,8192=0x2000
000003c0: 0501fff8 bgez $8,0x3a4
000003c4: 00000000 nop
000003c8: 03e00008 jr $31
000003cc: 00000000 nop
000003d0: 4009e000 mfc0 $9,R28
000003d4: 00000000 nop
000003d8: 240afc00 addiu $10,$0,-1024=0xfc00
000003dc: 012a4824 and $9,$9,$10
000003e0: 4089e000 mtc0 $9,R28
000003e4: 00000000 nop
000003e8: 40088001 mfc0 $8,R16.1
000003ec: 31090380 andi $9,$8,0x380
000003f0: 000949c2 srl $9,$9,7
000003f4: 21290001 addi $9,$9,1
000003f8: 310a1c00 andi $10,$8,0x1c00
000003fc: 000a5282 srl $10,$10,10
00000400: 214a0001 addi $10,$10,1
00000404: 310be000 andi $11,$8,0xe000
00000408: 000b5b42 srl $11,$11,13
0000040c: 24080040 addiu $8,$0,64=0x0040
00000410: 01685804 sllv $11,$8,$11
00000414: 24080001 addiu $8,$0,1
00000418: 01485004 sllv $10,$8,$10
0000041c: 11600008 beq $11,$0,0x440
00000420: 00000000 nop
00000424: 712b2802 mul $5,$9,$11
00000428: 3c048000 lui $4,0x8000
0000042c: bc890000 cache 9,0($4)
00000430: 008a2020 add $4,$4,$10
00000434: 20a5ffff addi $5,$5,-1=0xffff
00000438: 1ca0fffc bgtz $5,0x42c
0000043c: 00000000 nop
00000440: 40088001 mfc0 $8,R16.1
00000444: 3c010007 lui $1,0x7
00000448: 01014824 and $9,$8,$1
0000044c: 00094c02 srl $9,$9,16
00000450: 21290001 addi $9,$9,1
00000454: 3c010038 lui $1,0x38
00000458: 01015024 and $10,$8,$1
0000045c: 000a54c2 srl $10,$10,19
00000460: 3c0101c0 lui $1,0x1c0
00000464: 01015824 and $11,$8,$1
00000468: 000b5d82 srl $11,$11,22
0000046c: 214a0001 addi $10,$10,1
00000470: 24080040 addiu $8,$0,64=0x0040
00000474: 01685804 sllv $11,$8,$11
00000478: 24080001 addiu $8,$0,1
0000047c: 01485004 sllv $10,$8,$10
00000480: 11600008 beq $11,$0,0x4a4
00000484: 00000000 nop
00000488: 712b2802 mul $5,$9,$11
0000048c: 3c048000 lui $4,0x8000
00000490: bc800000 cache 0,0($4)
00000494: 008a2020 add $4,$4,$10
00000498: 20a5ffff addi $5,$5,-1=0xffff
0000049c: 1ca0fffc bgtz $5,0x490
000004a0: 00000000 nop
000004a4: 03e00008 jr $31
000004a8: 00000000 nop
000004ac: 3c10bfc0 lui $16,0xbfc0
000004b0: 36100800 ori $16,$16,0x800
000004b4: 3c11bfc0 lui $17,0xbfc0
000004b8: 36313000 ori $17,$17,0x3000
000004bc: 3c12a07e lui $18,0xa07e
000004c0: 8e080000 lw $8,0($16)
000004c4: ae480000 sw $8,0($18)
000004c8: 22100004 addi $16,$16,4
000004cc: 22520004 addi $18,$18,4
000004d0: 1611fffb bne $16,$17,0x4c0
000004d4: 00000000 nop
000004d8: 3c08807e lui $8,0x807e
000004dc: 00000000 nop
000004e0: 01000008 jr $8

/*
* Copyright © 2001-2002 Atheros Communications, Inc., All Rights Reserved
*/

/*
* Add support for Cobra
*
* AR2316reg.h Register definitions for Atheros AR5311 and AR2316 chipsets.
* - WLAN registers are listed in
* hal/ar5211/ar5211Reg.h
* hal/ar5212/ar5212Reg.h
* - Ethernet registers are listed in ar531xenet.h
* - Standard UART is 16550 compatible.
*/

#ifndef _AR2316REG_H
#define _AR2316REG_H

#ident "ACI $Header:
//depot/sw/releases/linux_5.3/src/redboot_cobra/ecos/packages/hal/mips/ar2316/current/include/ar2316reg.h#1 $"

/*
* Address map
*/
#define AR2316_SDRAM0 0x00000000 /* DRAM */
#define AR2316_SPI_READ 0x08000000 /* SPI FLASH */
#define AR2316_WLAN0 0xB0000000 /* Wireless MMR */
#define AR2316_PCI 0xB0100000 /* PCI MMR */
#define AR2316_SDRAMCTL 0xB0300000 /* SDRAM MMR */
#define AR2316_LOCAL 0xB0400000 /* LOCAL BUS MMR */
#define AR2316_ENET0 0xB0500000 /* ETHERNET MMR */
#define AR2316_DSLBASE 0xB1000000 /* RESET CONTROL MMR */
#define AR2316_UART0 0xB1100003 /* UART MMR */
#define AR2316_SPI 0xB1300000 /* SPI FLASH MMR */
#define AR2316_FLASHBT 0xBfc00000 /* ro boot alias to FLASH */
#define AR2316_RAM1 0x40000000 /* ram alias */
#define AR2316_PCIEXT 0x80000000 /* pci external */
#define AR2316_RAM2 0xc0000000 /* ram alias */
#define AR2316_RAM3 0xe0000000 /* ram alias */

/*
* Reset Register
*/
#define AR2316_COLD_RESET (AR2316_DSLBASE + 0x0000)

/* Cold Reset */
#define RESET_COLD_AHB 0x00000001
#define RESET_COLD_APB 0x00000002
#define RESET_COLD_CPU 0x00000004
#define RESET_COLD_CPUWARM 0x00000008
#define AR2317_RESET_SYSTEM 0x00000010
#define RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */

/* Warm Reset */

#define AR2316_RESET (AR2316_DSLBASE + 0x0004)

#define RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
#define RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
#define RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
#define RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
#define RESET_MEMCTL 0x00000010 /* warm reset memory controller */
#define RESET_LOCAL 0x00000020 /* warm reset local bus */
#define RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
#define RESET_SPI 0x00000080 /* warm reset SPI interface */
#define RESET_UART0 0x00000100 /* warm reset UART0 */
#define RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
#define RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
#define RESET_ENET0 0x00000800 /* cold reset ENET0 mac */

/*
* AHB master arbitration control
*/
#define AR2316_AHB_ARB_CTL (AR2316_DSLBASE + 0x0008)

#define ARB_CPU 0x00000001 /* CPU, default */
#define ARB_WLAN 0x00000002 /* WLAN */
#define ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
#define ARB_LOCAL 0x00000008 /* LOCAL */
#define ARB_PCI 0x00000010 /* PCI */
#define ARB_ETHERNET 0x00000020 /* Ethernet */
#define ARB_RETRY 0x00000100 /* retry policy, debug only */

/*
* Config Register
*/
#define AR2316_ENDIAN_CTL (AR2316_DSLBASE + 0x000c)

#define CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
#define CONFIG_WLAN 0x00000002 /* WLAN byteswap */
#define CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
#define CONFIG_PCI 0x00000008 /* PCI byteswap */
#define CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
#define CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
#define CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */

#define CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
#define CONFIG_CPU 0x00000400 /* CPU big endian */
#define CONFIG_PCIAHB 0x00000800
#define CONFIG_PCIAHB_BRIDGE 0x00001000
#define CONFIG_SPI 0x00008000 /* SPI byteswap */
#define CONFIG_CPU_DRAM 0x00010000
#define CONFIG_CPU_PCI 0x00020000
#define CONFIG_CPU_MMR 0x00040000
#define CONFIG_BIG 0x00000400


/*
* NMI control
*/
#define AR2316_NMI_CTL (AR2316_DSLBASE + 0x0010)

#define NMI_EN 1

/*
* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
*/
#define AR2316_SREV (AR2316_DSLBASE + 0x0014)

#define REV_MAJ 0x00f0
#define REV_MAJ_S 4
#define REV_MIN 0x000f
#define REV_MIN_S 0
#define REV_CHIP (REV_MAJ|REV_MIN)

/*
* Interface Enable
*/
#define AR2316_IF_CTL (AR2316_DSLBASE + 0x0018)

#define IF_MASK 0x00000007
#define IF_DISABLED 0
#define IF_PCI 1
#define IF_TS_LOCAL 2
#define IF_ALL 3 /* only for emulation with separate pins */
#define IF_LOCAL_HOST 0x00000008
#define IF_PCI_HOST 0x00000010
#define IF_PCI_INTR 0x00000020
#define IF_PCI_CLK_MASK 0x00030000
#define IF_PCI_CLK_INPUT 0
#define IF_PCI_CLK_OUTPUT_LOW 1
#define IF_PCI_CLK_OUTPUT_CLK 2
#define IF_PCI_CLK_OUTPUT_HIGH 3
#define IF_PCI_CLK_SHIFT 16


/* Major revision numbers, bits 7..4 of Revision ID register */
#define REV_MAJ_AR5311 0x01
#define REV_MAJ_AR5312 0x04
#define REV_MAJ_AR5315 0x0B

/*
* APB Interrupt control
*/

#define AR2316_ISR (AR2316_DSLBASE + 0x0020)
#define AR2316_IMR (AR2316_DSLBASE + 0x0024)
#define AR2316_GISR (AR2316_DSLBASE + 0x0028)

#define ISR_UART0 0x0001 /* high speed UART */
#define ISR_I2C_RSVD 0x0002 /* I2C bus */
#define ISR_SPI 0x0004 /* SPI bus */
#define ISR_AHB 0x0008 /* AHB error */
#define ISR_APB 0x0010 /* APB error */
#define ISR_TIMER 0x0020 /* timer */
#define ISR_GPIO 0x0040 /* GPIO */
#define ISR_WD 0x0080 /* watchdog */
#define ISR_IR_RSVD 0x0100 /* IR */

#define IMR_UART0 ISR_UART0
#define IMR_I2C_RSVD ISR_I2C_RSVD
#define IMR_SPI ISR_SPI
#define IMR_AHB ISR_AHB
#define IMR_APB ISR_APB
#define IMR_TIMER ISR_TIMER
#define IMR_GPIO ISR_GPIO
#define IMR_WD ISR_WD
#define IMR_IR_RSVD ISR_IR_RSVD

#define GISR_MISC 0x0001
#define GISR_WLAN0 0x0002
#define GISR_MPEGTS_RSVD 0x0004
#define GISR_LOCALPCI 0x0008
#define GISR_WMACPOLL 0x0010
#define GISR_TIMER 0x0020
#define GISR_ETHERNET 0x0040

/*
* Interrupt routing from IO to the processor IP bits
* Define our inter mask and level
*/
#define AR2316_INTR_MISCIO SR_IBIT3
#define AR2316_INTR_WLAN0 SR_IBIT4
#define AR2316_INTR_ENET0 SR_IBIT5
#define AR2316_INTR_LOCALPCI SR_IBIT6
#define AR2316_INTR_WMACPOLL SR_IBIT7
#define AR2316_INTR_COMPARE SR_IBIT8

/*
* Timers
*/
#define AR2316_TIMER (AR2316_DSLBASE + 0x0030)
#define AR2316_RELOAD (AR2316_DSLBASE + 0x0034)
#define AR2316_WD (AR2316_DSLBASE + 0x0038)
#define AR2316_WDC (AR2316_DSLBASE + 0x003c)

#define WDC_RESET 0x00000002 /* reset on watchdog */
#define WDC_NMI 0x00000001 /* NMI on watchdog */

/*
* Interface Debug
*/
#define AR531X_FLASHDBG (AR531X_RESETTMR + 0x0040)
#define AR531X_MIIDBG (AR531X_RESETTMR + 0x0044)


/*
* CPU Performance Counters
*/
#define AR2316_PERFCNT0 (AR2316_DSLBASE + 0x0048)
#define AR2316_PERFCNT1 (AR2316_DSLBASE + 0x004c)

#define PERF_DATAHIT 0x0001 /* Count Data Cache Hits */
#define PERF_DATAMISS 0x0002 /* Count Data Cache Misses */
#define PERF_INSTHIT 0x0004 /* Count Instruction Cache Hits */
#define PERF_INSTMISS 0x0008 /* Count Instruction Cache Misses */
#define PERF_ACTIVE 0x0010 /* Count Active Processor Cycles */
#define PERF_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
#define PERF_WBMISS 0x0040 /* Count CPU Write Buffer Misses */

#define PERF_EB_ARDY 0x0001 /* Count EB_ARdy signal */
#define PERF_EB_AVALID 0x0002 /* Count EB_AValid signal */
#define PERF_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
#define PERF_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
#define PERF_VRADDR 0x0010 /* Count valid read address cycles */
#define PERF_VWADDR 0x0020 /* Count valid write address cycles */
#define PERF_VWDATA 0x0040 /* Count valid write data cycles */

/*
* AHB Error Reporting.
*/
#define AR2316_AHB_ERR0 (AR2316_DSLBASE + 0x0050) /* error */
#define AR2316_AHB_ERR1 (AR2316_DSLBASE + 0x0054) /* haddr */
#define AR2316_AHB_ERR2 (AR2316_DSLBASE + 0x0058) /* hwdata */
#define AR2316_AHB_ERR3 (AR2316_DSLBASE + 0x005c) /* hrdata */
#define AR2316_AHB_ERR4 (AR2316_DSLBASE + 0x0060) /* status */

#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
/* write 1 to clear all bits in ERR0 */
#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */

#define PROCERR_HMAST 0x0000000f
#define PROCERR_HMAST_DFLT 0
#define PROCERR_HMAST_WMAC 1
#define PROCERR_HMAST_ENET 2
#define PROCERR_HMAST_PCIENDPT 3
#define PROCERR_HMAST_LOCAL 4
#define PROCERR_HMAST_CPU 5
#define PROCERR_HMAST_PCITGT 6

#define PROCERR_HMAST_S 0
#define PROCERR_HWRITE 0x00000010
#define PROCERR_HSIZE 0x00000060
#define PROCERR_HSIZE_S 5
#define PROCERR_HTRANS 0x00000180
#define PROCERR_HTRANS_S 7
#define PROCERR_HBURST 0x00000e00
#define PROCERR_HBURST_S 9



/*
* Clock Control
*/
#define AR2316_PLLC_CTL (AR2316_DSLBASE + 0x0064)
#define AR2316_PLLV_CTL (AR2316_DSLBASE + 0x0068)
#define AR2316_CPUCLK (AR2316_DSLBASE + 0x006c)
#define AR2316_AMBACLK (AR2316_DSLBASE + 0x0070)
#define AR2316_SYNCCLK (AR2316_DSLBASE + 0x0074)
#define AR2316_DSL_SLEEP_CTL (AR2316_DSLBASE + 0x0080)
#define AR2316_DSL_SLEEP_DUR (AR2316_DSLBASE + 0x0084)

/* PLLc Control fields */
#define PLLC_REF_DIV_M 0x00000003
#define PLLC_REF_DIV_S 0
#define PLLC_FDBACK_DIV_M 0x0000007C
#define PLLC_FDBACK_DIV_S 2
#define PLLC_ADD_FDBACK_DIV_M 0x00000080
#define PLLC_ADD_FDBACK_DIV_S 7
#define PLLC_CLKC_DIV_M 0x0001c000
#define PLLC_CLKC_DIV_S 14
#define PLLC_CLKM_DIV_M 0x00700000
#define PLLC_CLKM_DIV_S 20

/* CPU CLK Control fields */
#define CPUCLK_CLK_SEL_M 0x00000003
#define CPUCLK_CLK_SEL_S 0
#define CPUCLK_CLK_DIV_M 0x0000000c
#define CPUCLK_CLK_DIV_S 2

/* AMBA CLK Control fields */
#define AMBACLK_CLK_SEL_M 0x00000003
#define AMBACLK_CLK_SEL_S 0
#define AMBACLK_CLK_DIV_M 0x0000000c
#define AMBACLK_CLK_DIV_S 2

#if defined(COBRA_EMUL)
#define AR2316_AMBA_CLOCK_RATE 20000000
#define AR2316_CPU_CLOCK_RATE 40000000
#else
#if defined(DEFAULT_PLL)
#define AR2316_AMBA_CLOCK_RATE 40000000
#define AR2316_CPU_CLOCK_RATE 40000000
#else
#define AR2316_AMBA_CLOCK_RATE 92000000
#define AR2316_CPU_CLOCK_RATE 184000000
#endif /* ! DEFAULT_PLL */
#endif /* ! COBRA_EMUL */

#define AR2316_UART_CLOCK_RATE AR2316_AMBA_CLOCK_RATE
#define AR2316_SDRAM_CLOCK_RATE AR2316_AMBA_CLOCK_RATE

/*
* The UART computes baud rate as:
* baud = clock / (16 * divisor)
* where divisor is specified as a High Byte (DLM) and a Low Byte (DLL).
*/
#define DESIRED_BAUD_RATE 9600

/*
* The WATCHDOG value is computed as
* 10 seconds * AR531X_WATCHDOG_CLOCK_RATE
*/
#define DESIRED_WATCHDOG_SECONDS 10
#define AR531X_WATCHDOG_TIME \
(DESIRED_WATCHDOG_SECONDS * AR531X_WATCHDOG_CLOCK_RATE)


#define CLOCKCTL_UART0 0x0010 /* enable UART0 external clock */


/*
* Applicable "PCICFG" bits for WLAN(s). Assoc status and LED mode.
*/
#define AR531X_PCICFG (AR531X_RESETTMR + 0x00b0)
#define ASSOC_STATUS_M 0x00000003
#define ASSOC_STATUS_NONE 0
#define ASSOC_STATUS_PENDING 1
#define ASSOC_STATUS_ASSOCIATED 2
#define LED_MODE_M 0x0000001c
#define LED_BLINK_THRESHOLD_M 0x000000e0
#define LED_SLOW_BLINK_MODE 0x00000100

/*
* GPIO
*/

#define AR2316_GPIO_DI (AR2316_DSLBASE + 0x0088)
#define AR2316_GPIO_DO (AR2316_DSLBASE + 0x0090)
#define AR2316_GPIO_CR (AR2316_DSLBASE + 0x0098)
#define AR2316_GPIO_INT (AR2316_DSLBASE + 0x00a0)

#define GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
#define GPIO_CR_O(x) (1 << (x)) /* output */
#define GPIO_CR_I(x) (0 << (x)) /* input */

#define GPIO_INT(x,Y) ((x) << (8 * (Y))) /* interrupt enable */
#define GPIO_INT_M(Y) ((0x3F) << (8 * (Y))) /* mask for int */
#define GPIO_INT_LVL(x,Y) ((x) << (8 * (Y) + 6)) /* interrupt level */
#define GPIO_INT_LVL_M(Y) ((0x3) << (8 * (Y) + 6)) /* mask for int level */

#define AR2316_RESET_GPIO 5
#define AR2316_NUM_GPIO 22


/*
* PCI Clock Control
*/

#define AR2316_PCICLK (AR2316_DSLBASE + 0x00a4)

#define PCICLK_INPUT_M 0x3
#define PCICLK_INPUT_S 0

#define PCICLK_PLLC_CLKM 0
#define PCICLK_PLLC_CLKM1 1
#define PCICLK_PLLC_CLKC 2
#define PCICLK_REF_CLK 3

#define PCICLK_DIV_M 0xc
#define PCICLK_DIV_S 2

#define PCICLK_IN_FREQ 0
#define PCICLK_IN_FREQ_DIV_6 1
#define PCICLK_IN_FREQ_DIV_8 2
#define PCICLK_IN_FREQ_DIV_10 3

/*
* Observation Control Register
*/
#define AR2316_OCR (AR2316_DSLBASE + 0x00b0)
#define OCR_GPIO0_IRIN 0x0040
#define OCR_GPIO1_IROUT 0x0080
#define OCR_GPIO3_RXCLR 0x0200

/*
* General Clock Control
*/

#define AR2316_MISCCLK (AR2316_DSLBASE + 0x00b4)
#define MISCCLK_PLLBYPASS_EN 0x00000001
#define MISCCLK_PROCREFCLK 0x00000002

/*
* SDRAM Controller
* - No read or write buffers are included.
*/
#define AR2316_MEM_CFG (AR2316_SDRAMCTL + 0x00)
#define AR2316_MEM_STMGOR (AR2316_SDRAMCTL + 0x04)
#define AR2316_MEM_CTRL (AR2316_SDRAMCTL + 0x0c)
#define AR2316_MEM_REF (AR2316_SDRAMCTL + 0x10)

#define SDRAM_DATA_WIDTH_M 0x00006000
#define SDRAM_DATA_WIDTH_S 13

#define SDRAM_COL_WIDTH_M 0x00001E00
#define SDRAM_COL_WIDTH_S 9

#define SDRAM_ROW_WIDTH_M 0x000001E0
#define SDRAM_ROW_WIDTH_S 5

#define SDRAM_BANKADDR_BITS_M 0x00000018
#define SDRAM_BANKADDR_BITS_S 3


/*
* SDRAM Memory Refresh (MEM_REF) value is computed as:
* MEMCTL_SREFR = (Tr * hclk_freq) / R
* where Tr is max. time of refresh of any single row
* R is number of rows in the DRAM
* For most 133MHz SDRAM parts, Tr=64ms, R=4096 or 8192
*/
#if defined(COBRA_EMUL)
#define AR2316_SDRAM_MEMORY_REFRESH_VALUE 0x96
#else
#if defined(DEFAULT_PLL)
#define AR2316_SDRAM_MEMORY_REFRESH_VALUE 0x200
#else
#define AR2316_SDRAM_MEMORY_REFRESH_VALUE 0x61a
#endif /* ! DEFAULT_PLL */
#endif

#if defined(AR2316)

#define AR2316_SDRAM_DDR_SDRAM 0 /* Not DDR SDRAM */
#define AR2316_SDRAM_DATA_WIDTH 16 /* bits */
#define AR2316_SDRAM_COL_WIDTH 8
#define AR2316_SDRAM_ROW_WIDTH 12

#else

#define AR2316_SDRAM_DDR_SDRAM 0 /* Not DDR SDRAM */
#define AR2316_SDRAM_DATA_WIDTH 16
#define AR2316_SDRAM_COL_WIDTH 8
#define AR2316_SDRAM_ROW_WIDTH 12

#endif /* ! AR2316 */

/*
* SPI Flash Interface Registers
*/

#define AR2316_SPI_CTL (AR2316_SPI + 0x00)
#define AR2316_SPI_OPCODE (AR2316_SPI + 0x04)
#define AR2316_SPI_DATA (AR2316_SPI + 0x08)

#define SPI_CTL_START 0x00000100
#define SPI_CTL_BUSY 0x00010000
#define SPI_CTL_TXCNT_MASK 0x0000000f
#define SPI_CTL_RXCNT_MASK 0x000000f0
#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
#define SPI_CTL_SIZE_MASK 0x00060000

#define SPI_CTL_CLK_SEL_MASK 0x03000000
#define SPI_OPCODE_MASK 0x000000ff

/*
* PCI-MAC Configuration registers
*/
#define PCI_MAC_RC (AR2316_PCI + 0x4000)
#define PCI_MAC_SCR (AR2316_PCI + 0x4004)
#define PCI_MAC_INTPEND (AR2316_PCI + 0x4008)
#define PCI_MAC_SFR (AR2316_PCI + 0x400C)
#define PCI_MAC_PCICFG (AR2316_PCI + 0x4010)
#define PCI_MAC_SREV (AR2316_PCI + 0x4020)

#define PCI_MAC_RC_MAC 0x00000001
#define PCI_MAC_RC_BB 0x00000002

#define PCI_MAC_SCR_SLMODE_M 0x00030000
#define PCI_MAC_SCR_SLMODE_S 16
#define PCI_MAC_SCR_SLM_FWAKE 0
#define PCI_MAC_SCR_SLM_FSLEEP 1
#define PCI_MAC_SCR_SLM_NORMAL 2

#define PCI_MAC_SFR_SLEEP 0x00000001

#define PCI_MAC_PCICFG_SPWR_DN 0x00010000

/*
* WLAN MAC Configuration Registers
*/
#define AR2316_WLANPHY_BASE (AR2316_WLAN0 + 0x9800)

/*
* PCI Bus Interface Registers
*/
#define AR2316_PCI_1MS_REG (AR2316_PCI + 0x0008)
#define AR2316_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */

#define AR2316_PCI_MISC_CONFIG (AR2316_PCI + 0x000c)
#define AR2316_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
#define AR2316_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
#define AR2316_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
#define AR2316_PCIMISC_RST_MODE 0x00000030
#define AR2316_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
#define AR2316_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
#define AR2316_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
#define AR2316_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
#define AR2316_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
#define AR2316_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
#define AR2316_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
#define AR2316_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */

#define AR2316_PCI_OUT_TSTAMP (AR2316_PCI + 0x0010)

#define AR2316_PCI_UNCACHE_CFG (AR2316_PCI + 0x0014)

#define AR2316_PCI_IN_EN (AR2316_PCI + 0x0100)
#define AR2316_PCI_IN_EN0 0x01 /* Enable chain 0 */
#define AR2316_PCI_IN_EN1 0x02 /* Enable chain 1 */
#define AR2316_PCI_IN_EN2 0x04 /* Enable chain 2 */
#define AR2316_PCI_IN_EN3 0x08 /* Enable chain 3 */

#define AR2316_PCI_IN_DIS (AR2316_PCI + 0x0104)
#define AR2316_PCI_IN_DIS0 0x01 /* Disable chain 0 */
#define AR2316_PCI_IN_DIS1 0x02 /* Disable chain 1 */
#define AR2316_PCI_IN_DIS2 0x04 /* Disable chain 2 */
#define AR2316_PCI_IN_DIS3 0x08 /* Disable chain 3 */

#define AR2316_PCI_IN_PTR (AR2316_PCI + 0x0200)

#define AR2316_PCI_OUT_EN (AR2316_PCI + 0x0400)
#define AR2316_PCI_OUT_EN0 0x01 /* Enable chain 0 */

#define AR2316_PCI_OUT_DIS (AR2316_PCI + 0x0404)
#define AR2316_PCI_OUT_DIS0 0x01 /* Disable chain 0 */

#define AR2316_PCI_OUT_PTR (AR2316_PCI + 0x0408)

#define AR2316_PCI_INT_STATUS (AR2316_PCI + 0x0500) /* write one to clr */
#define AR2316_PCI_TXINT 0x00000001 /* Desc In Completed */
#define AR2316_PCI_TXOK 0x00000002 /* Desc In OK */
#define AR2316_PCI_TXERR 0x00000004 /* Desc In ERR */
#define AR2316_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
#define AR2316_PCI_RXINT 0x00000010 /* Desc Out Completed */
#define AR2316_PCI_RXOK 0x00000020 /* Desc Out OK */
#define AR2316_PCI_RXERR 0x00000040 /* Desc Out ERR */
#define AR2316_PCI_RXEOL 0x00000080 /* Desc Out EOL */
#define AR2316_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
#define AR2316_PCI_MASK 0x0000FFFF /* Desc Mask */
#define AR2316_PCI_EXT_INT 0x02000000
#define AR2316_PCI_ABORT_INT 0x04000000

#define AR2316_PCI_INT_MASK (AR2316_PCI + 0x0504) /* same as INT_STATUS */

#define AR2316_PCI_INTEN_REG (AR2316_PCI + 0x0508)
#define AR2316_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
#define AR2316_PCI_INT_ENABLE 0x01 /* enable pci interrupts */

#define AR2316_PCI_HOST_IN_EN (AR2316_PCI + 0x0800)
#define AR2316_PCI_HOST_IN_DIS (AR2316_PCI + 0x0804)
#define AR2316_PCI_HOST_IN_PTR (AR2316_PCI + 0x0810)
#define AR2316_PCI_HOST_OUT_EN (AR2316_PCI + 0x0900)
#define AR2316_PCI_HOST_OUT_DIS (AR2316_PCI + 0x0904)
#define AR2316_PCI_HOST_OUT_PTR (AR2316_PCI + 0x0908)


/*
* Local Bus Interface Registers
*/
#define AR2316_LB_CONFIG (AR2316_LOCAL + 0x0000)
#define AR2316_LBCONF_OE 0x00000001 /* =1 OE is low-true */
#define AR2316_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
#define AR2316_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
#define AR2316_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
#define AR2316_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
#define AR2316_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
#define AR2316_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
#define AR2316_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
#define AR2316_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
#define AR2316_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
#define AR2316_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
#define AR2316_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
#define AR2316_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
#define AR2316_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
#define AR2316_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
#define AR2316_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
#define AR2316_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
#define AR2316_LBCONF_INT 0x00020000 /* =1 Intr is low true */
#define AR2316_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
#define AR2316_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
#define AR2316_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
#define AR2316_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
#define AR2316_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
#define AR2316_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
#define AR2316_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */

#define AR2316_LB_CLKSEL (AR2316_LOCAL + 0x0004)
#define AR2316_LBCLK_EXT 0x0001 /* use external clk for lb */

#define AR2316_LB_1MS (AR2316_LOCAL + 0x0008)
#define AR2316_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */

#define AR2316_LB_MISCCFG (AR2316_LOCAL + 0x000C)
#define AR2316_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
#define AR2316_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
#define AR2316_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
#define AR2316_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
#define AR2316_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
#define AR2316_LBM_TIMEOUT_MASK 0x00FFFF80
#define AR2316_LBM_TIMEOUT_SHFT 7
#define AR2316_LBM_PORTMUX 0x07000000


#define AR2316_LB_RXTSOFF (AR2316_LOCAL + 0x0010)

#define AR2316_LB_TX_CHAIN_EN (AR2316_LOCAL + 0x0100)
#define AR2316_LB_TXEN_0 0x01
#define AR2316_LB_TXEN_1 0x02
#define AR2316_LB_TXEN_2 0x04
#define AR2316_LB_TXEN_3 0x08

#define AR2316_LB_TX_CHAIN_DIS (AR2316_LOCAL + 0x0104)
#define AR2316_LB_TX_DESC_PTR (AR2316_LOCAL + 0x0200)

#define AR2316_LB_RX_CHAIN_EN (AR2316_LOCAL + 0x0400)
#define AR2316_LB_RXEN 0x01

#define AR2316_LB_RX_CHAIN_DIS (AR2316_LOCAL + 0x0404)
#define AR2316_LB_RX_DESC_PTR (AR2316_LOCAL + 0x0408)

#define AR2316_LB_INT_STATUS (AR2316_LOCAL + 0x0500)
#define AR2316_INT_TX_DESC 0x0001
#define AR2316_INT_TX_OK 0x0002
#define AR2316_INT_TX_ERR 0x0004
#define AR2316_INT_TX_EOF 0x0008
#define AR2316_INT_RX_DESC 0x0010
#define AR2316_INT_RX_OK 0x0020
#define AR2316_INT_RX_ERR 0x0040
#define AR2316_INT_RX_EOF 0x0080
#define AR2316_INT_TX_TRUNC 0x0100
#define AR2316_INT_TX_STARVE 0x0200
#define AR2316_INT_LB_TIMEOUT 0x0400
#define AR2316_INT_LB_ERR 0x0800
#define AR2316_INT_MBOX_WR 0x1000
#define AR2316_INT_MBOX_RD 0x2000

/* Bit definitions for INT MASK are the same as INT_STATUS */
#define AR2316_LB_INT_MASK (AR2316_LOCAL + 0x0504)

#define AR2316_LB_INT_EN (AR2316_LOCAL + 0x0508)
#define AR2316_LB_MBOX (AR2316_LOCAL + 0x0600)



/*
* IR Interface Registers
*/
#define AR2316_IR_PKTDATA (AR2316_IR + 0x0000)

#define AR2316_IR_PKTLEN (AR2316_IR + 0x07fc) /* 0 - 63 */

#define AR2316_IR_CONTROL (AR2316_IR + 0x0800)
#define AR2316_IRCTL_TX 0x00000000 /* use as tranmitter */
#define AR2316_IRCTL_RX 0x00000001 /* use as receiver */
#define AR2316_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
#define AR2316_IRCTL_SAMPLECLK_SHFT 1
#define AR2316_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
#define AR2316_IRCTL_OUTPUTCLK_SHFT 14

#define AR2316_IR_STATUS (AR2316_IR + 0x0804)
#define AR2316_IRSTS_RX 0x00000001 /* receive in progress */
#define AR2316_IRSTS_TX 0x00000002 /* transmit in progress */

#define AR2316_IR_CONFIG (AR2316_IR + 0x0808)
#define AR2316_IRCFG_INVIN 0x00000001 /* invert input polarity */
#define AR2316_IRCFG_INVOUT 0x00000002 /* invert output polarity */
#define AR2316_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
#define AR2316_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
#define AR2316_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
#define AR2316_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
#define AR2316_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
#define AR2316_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
#define AR2316_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */

/*
* PCI memory constants: Memory area 1 and 2 are the same size -
* (twice the PCI_TLB_PAGE_SIZE). The definition of
* CPU_TO_PCI_MEM_SIZE is coupled with the TLB setup routine
* sysLib.c/sysTlbInit(), in that it assumes that 2 pages of size
* PCI_TLB_PAGE_SIZE are set up in the TLB for each PCI memory space.
*/

#define CPU_TO_PCI_MEM_BASE1 0xE0000000
#define CPU_TO_PCI_MEM_SIZE1 (2*PCI_TLB_PAGE_SIZE)


/* TLB attributes for PCI transactions */

#define PCI_MMU_PAGEMASK 0x00003FFF
#define MMU_PAGE_UNCACHED 0x00000010
#define MMU_PAGE_DIRTY 0x00000004
#define MMU_PAGE_VALID 0x00000002
#define MMU_PAGE_GLOBAL 0x00000001
#define PCI_MMU_PAGEATTRIB (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY|\
MMU_PAGE_VALID|MMU_PAGE_GLOBAL)
#define PCI_MEMORY_SPACE1_VIRT 0xE0000000 /* Used for non-prefet mem */
#define PCI_MEMORY_SPACE1_PHYS 0x80000000
#define PCI_TLB_PAGE_SIZE 0x01000000
#define TLB_HI_MASK 0xFFFFE000
#define TLB_LO_MASK 0x3FFFFFFF
#define PAGEMASK_SHIFT 11
#define TLB_LO_SHIFT 6

#define PCI_MAX_LATENCY 0xFFF /* Max PCI latency */

#define HOST_PCI_DEV_ID 3
#define HOST_PCI_MBAR0 0x10000000
#define HOST_PCI_MBAR1 0x20000000
#define HOST_PCI_MBAR2 0x30000000

#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
#define PCI_DEVICE_MEM_SPACE 0x800000

#endif