void ssc_start_i2s(void)
{
audio_pll_sw(1); // Switch to I2S clock

AT91C_BASE_PMC->PMC_PCER = 1UL << AT91C_ID_SSC;

AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;

AT91C_BASE_SSC->SSC_CMR = 16; // MCK / 32

// PERIOD: 32, STTDLY: 1, START: falling edge on TF, CKO: continuous, CKS: TK
AT91C_BASE_SSC->SSC_TCMR = (15 << 24) | (1 << 16) | AT91C_SSC_START_FALL_RF | AT91C_SSC_CKO_CONTINOUS | AT91C_SSC_CKS_DIV;
// FSOS: negative pulse on TF, DATNB: 1, MSB first, 16 bits
AT91C_BASE_SSC->SSC_TFMR = AT91C_SSC_FSOS_NEGATIVE | (15 << 16) | (1 << 8) | AT91C_SSC_MSBF | 15;

AT91C_BASE_SSC->SSC_TPR = (u_int)&audio_tx_buffer[0][0];
AT91C_BASE_SSC->SSC_TCR = AUDIO_BUFFER_SAMPLES_PER_CH * 2;
AT91C_BASE_SSC->SSC_TNPR = (u_int)&audio_tx_buffer[1][0];
AT91C_BASE_SSC->SSC_TNCR = AUDIO_BUFFER_SAMPLES_PER_CH * 2;
AT91C_BASE_SSC->SSC_PTCR = AT91C_PDC_TXTEN;

AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SSC] = PRIOR_SSC;
AT91C_BASE_AIC->AIC_SVR[AT91C_ID_SSC] = (u_int)ssc_irq_handler;
AT91C_BASE_AIC->AIC_IECR = 1UL << AT91C_ID_SSC;

AT91C_BASE_SSC->SSC_IER = AT91C_SSC_ENDTX;

AT91C_BASE_SSC->SSC_CR = AT91C_SSC_TXEN;

*AT91C_PMC_SCER = AT91C_PMC_PCK1; // Enable MCLK
}

#define SLOT_BY_FRAME 2
#define BITS_BY_SLOT 16
#define FILE_SAMPLING_FREQ 48000

#define IRQ_LEVEL_I2S    5





void dac_init(void)
{    
///Clock 12 Mhz
    AT91PS_PMC pPMC = AT91C_BASE_PMC;

    pPMC->PMC_PCKR[2] = (AT91C_PMC_PRES_CLK | AT91C_PMC_CSS_MAIN_CLK);
    *AT91C_PMC_SCER = AT91C_PMC_PCK2;
    while( !(*AT91C_PMC_SR & AT91C_PMC_PCK2RDY) );
    *AT91C_PIOA_BSR = AT91C_PA31_PCK2;
    *AT91C_PIOA_PDR = AT91C_PA31_PCK2;
///SSC init
*AT91C_PIOA_PDR = AT91C_PA16_TK | AT91C_PA15_TF | AT91C_PA17_TD;
AT91F_SSC_CfgPMC();
*AT91C_SSC_CR = AT91C_SSC_SWRST;

AT91F_PDC_Close((AT91PS_PDC) & (AT91C_BASE_SSC->SSC_RPR));

AT91F_SSC_SetBaudrate(AT91C_BASE_SSC,MCK,FILE_SAMPLING_FREQ*(BITS_BY_SLOT*SLOT_BY_FRAME));

*AT91C_SSC_TFMR = (AT91C_SSC_FSOS_NEGATIVE | (((BITS_BY_SLOT-1)<<16) & AT91C_SSC_FSLEN)
         | (((SLOT_BY_FRAME-1)<<8) & AT91C_SSC_DATNB) | AT91C_SSC_MSBF | (BITS_BY_SLOT-1) );

*AT91C_SSC_TCMR = (((((BITS_BY_SLOT*SLOT_BY_FRAME)/2) -1) <<24) | ((1<<16) & AT91C_SSC_STTDLY) |
            AT91C_SSC_START_FALL_RF | AT91C_SSC_CKO_CONTINOUS| AT91C_SSC_CKS_DIV);

AT91F_PDC_SetTx ((AT91PS_PDC) &(AT91C_BASE_SSC->SSC_RPR),        // PDC SSC base address
                     (char *)wav_file,    // pointer to data
                     wav_size/2);// Number of 16 bits words

AT91F_PDC_SetNextTx ((AT91PS_PDC) &(AT91C_BASE_SSC->SSC_RPR),    // PDC SSC base address
                         (char *)wav_file,     // pointer to next data
                         wav_size/2);

*AT91C_SSC_PTCR = AT91C_PDC_TXTEN;
*AT91C_SSC_PTSR == AT91C_PDC_TXTEN;

AT91F_SSC_EnableTx (AT91C_BASE_SSC);

}

AT91F_SSC_SetBaudrate(AT91C_BASE_SSC,MCK,FILE_SAMPLING_FREQ*(BITS_BY_SLOT*SLOT_BY_FRAME));

#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
#define MCK             45158400   // MCK (PLLRC )

//cs_startup.c
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x14) |
                      (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                      (AT91C_CKGR_MUL & (48<<16)));

//dac.c

//Clock 11.2896 Mhz
AT91PS_PMC pPMC = AT91C_BASE_PMC;
pPMC->PMC_PCKR[2] = (AT91C_PMC_PRES_CLK_4 | AT91C_PMC_CSS_PLL_CLK);
*AT91C_PMC_SCER = AT91C_PMC_PCK2;
while( !(*AT91C_PMC_SR & AT91C_PMC_PCK2RDY) );
*AT91C_PIOA_BSR = AT91C_PA18_PCK2;
*AT91C_PIOA_PDR = AT91C_PA18_PCK2;
    ///SSC init
*AT91C_PMC_PCER = (1 << AT91C_ID_SSC); // Enable Clock for SSC controller
*AT91C_SSC_CR = AT91C_SSC_SWRST; // reset
*AT91C_SSC_CMR = 16;
*AT91C_PIOA_PDR = AT91C_PA16_TK | AT91C_PA15_TF | AT91C_PA17_TD;

*AT91C_SSC_TCMR = (15 << 24) | (1 << 16) | AT91C_SSC_START_FALL_RF | AT91C_SSC_CKO_CONTINOUS | AT91C_SSC_CKS_DIV;
// FSOS: negative pulse on TF, DATNB: 1, MSB first, 16 bits
*AT91C_SSC_TFMR = AT91C_SSC_FSOS_NEGATIVE | (16 << 16) | (1 << 8) | AT91C_SSC_MSBF | 15;

*AT91C_SSC_TCMR = (15 << 24) | (0 << 16) | AT91C_SSC_START_FALL_RF | AT91C_SSC_CKO_CONTINOUS | AT91C_SSC_CKS_DIV;
*AT91C_SSC_TFMR = AT91C_SSC_FSOS_NEGATIVE | (15 << 16) | (1 << 8) | AT91C_SSC_MSBF | 15;