# Reference clock contraint for GTX
NET GTXQ4_left_i PERIOD = 8.0 ns HIGH 50%;

# User Clock Contraint: the value is selected based on the line rate (3125Mbps) of the module
NET "user_clk_i" TNM_NET = USER_CLK;
TIMESPEC TS_user_clk_i = PERIOD "USER_CLK" 15.0 ns HIGH 50%;

NET GTXQ4_P LOC=H6;
NET GTXQ4_N LOC=H5;

# 50MHz board Clock Constraint
NET "reset_logic_i/init_clk_i" TNM_NET = INIT_CLK;
TIMESPEC TS_INIT_CLK = PERIOD "INIT_CLK" 15.0 ns HIGH 50%;

NET INIT_CLK LOC = U23; # U23 - 66Mhz clock source on ml605 # 200MHz - J9;



###### No cross clock domain analysis. Domains are not related ##############
TIMESPEC "TS_TIG1" = FROM "INIT_CLK" TO "USER_CLK" TIG;

################################ Resets Buttons #################################
NET RESET LOC=G26; #BUTTON #NET "GPIO_SW_C" LOC = "G26"; ## 2 on SW9 pushbutton (active-High)
NET RESET PULLUP;
NET GT_RESET_IN LOC=A18; #BUTTON #NET "GPIO_SW_S" LOC = "A18"; ## 2 on SW6 pushbutton (active-High)

################################ Errors Indicators ##############################
NET HARD_ERROR LOC=AE22; #LED #NET "GPIO_LED_2" LOC = "AE22"; ## 2 on LED DS9, 3 on J62
NET SOFT_ERROR LOC=AE23; #LED #NET "GPIO_LED_3" LOC = "AE23"; ## 2 on LED DS10, 4 on J62
NET FRAME_ERROR LOC=AB23; #LED #NET "GPIO_LED_4" LOC = "AB23"; ## 2 on LED DS15, 5 on J62

################################ Channel and Lane up Indicators #################
#This board supports a maximum of 12 lanes
NET CHANNEL_UP LOC=AC22; #LED #NET "GPIO_LED_0" LOC = "AC22"; ## 2 on LED DS12, 1 on J62
NET LANE_UP LOC=AC24; #LED #NET "GPIO_LED_1" LOC = "AC24"; ## 2 on LED DS11, 2 on J62
################################################################################
#######
NET frame_check_i/* TIG;
################################################################################
#######
INST aurora_module_i/gtx_wrapper_i/GTXE1_INST/gtxe1_i LOC=GTXE1_X0Y18;