//------------------------------------------------------------------------------------------------------
// Self synchronous scrambler
//------------------------------------------------------------------------------------------------------

module scrambler
#(
parameter int pTYPE = 23, // 5/6/7/8/9/10/11/15/16/17/18/20/21/22/23/33/43
parameter int pWIDTH = 1,
parameter bit pMSB_FIRST = 0 // 1/0 :: first scrambled bit is MSB/LSB
)
(
iclk ,
iena ,
ibyp ,
idat ,
odat ,
oena
);

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

input wire iclk;
input wire iena;
input wire ibyp; // bypass data or not
input wire [pWIDTH-1 : 0] idat;
output logic [pWIDTH-1 : 0] odat;
output logic oena;

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
typedef logic [pWIDTH-1 : 0] data_t;
typedef logic [pTYPE : 1] state_t;

state_t state;
//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
// synthesis translate_off
initial begin : ini
odat = '0;
oena = '0;
state = '0;
end
// synthesis translate_on
//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------
generate
if (
(pTYPE == 5) || (pTYPE == 6) || (pTYPE == 7) || (pTYPE == 8) || (pTYPE == 9) ||
(pTYPE == 10) || (pTYPE == 11) || (pTYPE == 15) || (pTYPE == 16) || (pTYPE == 17) || (pTYPE == 18) ||
(pTYPE == 20) || (pTYPE == 21) || (pTYPE == 22) || (pTYPE == 23) ||
(pTYPE == 33) || (pTYPE == 43)
) begin
always_ff @(posedge iclk) begin
if (iena) begin
if (ibyp)
{state, odat} <= {'0, idat};
else
ScramblerWord(idat, state, odat);
end
oena <= iena;
end
end
else begin
assign state[-1] = 1'bx; // incorrect scrambler type is set
end
endgenerate

//------------------------------------------------------------------------------------------------------
// 5bit : x^5 + x^3 + 1
// 6bit : x^6 + x^5 + 1
// 7bit : x^7 + x^6 + 1
// 8bit : x^8 + x^6 + x^5 + x^4 + 1
// 9bit : x^9 + x^5 + 1
// 10bit : x^10 + x^7 + 1
// 11bit : x^11 + x^9 + 1
// 15bit : x^15 + x^14 + 1
// 16bit : x^16 + x^15 + x^13 + x^4 + 1
// 17bit : x^17 + x^14 + 1
// 18bit : x^18 + x^11 + 1
// 20bit : x^20 + x^17 + 1
// 21bit : x^21 + x^19 + 1
// 22bit : x^22 + x^21 + 1
// 23bit : x^23 + x^18 + 1
// 33bit : x^33 + x^20 + 1
// 43bit : x^43 + x^41 + x^20 + x + 1
//------------------------------------------------------------------------------------------------------

task automatic ScramblerBit(input bit b, inout state_t state, output bit msb);
case (pTYPE)
5 : msb = state[5] ^ state[3] ^ b;
6 : msb = state[6] ^ state[5] ^ b;
7 : msb = state[7] ^ state[6] ^ b;
8 : msb = state[8] ^ state[6] ^ state[5] ^ state[4] ^ b;
9 : msb = state[9] ^ state[5] ^ b;
10 : msb = state[10] ^ state[7] ^ b;
11 : msb = state[11] ^ state[9] ^ b;
15 : msb = state[15] ^ state[14] ^ b;
16 : msb = state[16] ^ state[15] ^ state[13] ^ state[4] ^ b;
17 : msb = state[17] ^ state[14] ^ b;
18 : msb = state[18] ^ state[11] ^ b;
20 : msb = state[20] ^ state[17] ^ b;
21 : msb = state[21] ^ state[19] ^ b;
22 : msb = state[22] ^ state[21] ^ b;
23 : msb = state[23] ^ state[18] ^ b;
33 : msb = state[33] ^ state[20] ^ b;
43 : msb = state[43] ^ state[41] ^ state[20] ^ state[1] ^ b;
default : msb = 1'b0;
endcase
state = (state << 1) | msb;
endtask

//------------------------------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------------------------------

task automatic ScramblerWord (input data_t b, inout state_t state, output data_t msb);
int i;
begin
if (pMSB_FIRST == 0) begin
for (i = 0; i < $size(; i++) ScramblerBit (b[i], state, msb[i]);
end
else begin // pMSB_FIRST == 1
for (i = $high(; i >= 0; i--) ScramblerBit (b[i], state, msb[i]);
end
end
endtask

endmodule

while(flag == 1'b0)        repeat (1) @(negedge clk);