alt_u16 eth_phy_get_config (alt_u8 reg_address)
{
alt_u16 mdio_request = 0;
alt_u16 mdio_request_blank = 0x1980;
alt_u16 mdio_readdata = 0;
int i;
int tmp;

mdio_request = mdio_request_blank | ((alt_u16)((reg_address)&0x1f));

IOWR_ETH_CONTROL_MDIO_OPCODE(ETH_CONTROL_BASE, ETH_MDIO_OP_WRITE);

tmp = IORD_ETH_CONTROL_MDIO_READ_DATA(ETH_CONTROL_BASE) & ETH_CONTROL_MDIO_DATA_MSK;

for (i = 0; i < 14; i++)
{
tmp = (mdio_request >> (13-i)) & ETH_CONTROL_MDIO_DATA_MSK;
IOWR_ETH_CONTROL_MDIO_WRITE_DATA(ETH_CONTROL_BASE, tmp);
IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,1);
IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,0);
}

IOWR_ETH_CONTROL_MDIO_OPCODE(ETH_CONTROL_BASE, ETH_MDIO_OP_READ);

for (i = 0; i< 2; i++)
{
IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,1);
IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,0);
if (i==1) tmp = IORD_ETH_CONTROL_MDIO_READ_DATA(ETH_CONTROL_BASE) & ETH_CONTROL_MDIO_DATA_MSK;
}

for (i = 0; i<16; i++)
{
IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,1);
IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,0);

mdio_readdata = mdio_readdata | ((IORD_ETH_CONTROL_MDIO_READ_DATA(ETH_CONTROL_BASE) & ETH_CONTROL_MDIO_DATA_MSK) << (15 - i));
}

return mdio_readdata;
}

assign MDIO = (mdio_opcode_r) ? mdio_data_r : 1'hz

    IOWR_ETH_CONTROL_MDIO_OPCODE(ETH_CONTROL_BASE, ETH_MDIO_OP_WRITE); // выставить значение mdc_opcode на 1

    for (i = 0; i < 14; i++)
    {
        tmp = (mdio_request >> (13-i)) & ETH_CONTROL_MDIO_DATA_MSK;
        IOWR_ETH_CONTROL_MDIO_WRITE_DATA(ETH_CONTROL_BASE, tmp);     //  выставить следующий бит посылки
        IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,1);              //   изменить значение mdc на 1
        IOWR_ETH_CONTROL_MDIO_MDC_CLK(ETH_CONTROL_BASE,0);              //  изменить значение mdc на 0
    }

//*********************** MIIM_MDIO *************************/

always @ (posedge clk or negedge rst)
begin
if(!rst)
mdio_opcode_r <= 1'b0;
else
if ((chipselect) && (ctrl_write) && (ctrl_address == MDIO_OPCODE))
mdio_opcode_r <= ctrl_writedata[0];
else
mdio_opcode_r <= mdio_opcode_r;
end

always @ (posedge clk or negedge rst)
begin
if (!rst)
mdio_data_r <= 1'b0;
else
if ((chipselect) && (ctrl_write) && (ctrl_address == MDIO_DATA))
mdio_data_r <= ctrl_writedata[0];
else
mdio_data_r <= mdio_data_r;
end

assign MDIO = (mdio_opcode_r) ? mdio_data_r : 1'bz;

always @(posedge clk or negedge rst)
begin
if(!rst)
mdio_clk_r <= 1'b0;
else
if ((chipselect) && (ctrl_write) && (ctrl_address == MDIO_DATA_CLK))
mdio_clk_r <= ctrl_writedata[0];
else
mdio_clk_r <= mdio_clk_r;
end

assign MDC = mdio_clk_r;

//****************** AVALON-MM_READ_INTERFACE *****************/
always @(posedge clk or negedge rst)
begin
if(!rst)
ctrl_readdata_r <= 32'b0;
else
if (chipselect & ctrl_read)
case (ctrl_address)
RX_RECEIVED_BYTES: ctrl_readdata_r <= {21'b0, rx_bite_count_clk_r};
TX_READY: ctrl_readdata_r <= {31'b0, tx_ready_clk_r};
MDIO_DATA: ctrl_readdata_r <= {31'b0, MDIO};
endcase
else
ctrl_readdata_r <= 32'd0;
end

assign ctrl_readdata = ctrl_readdata_r;