Xuint32 *tst3 = (Xuint32 *)0x00240000;
*(tst3 + 100) = 12;

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = DCM0
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT1_PHASE = 90
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
PORT CLKOUT1 = sys_clk_90_s
END

BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM
PARAMETER HW_VER = 4.03.a
PARAMETER C_NUM_PORTS = 2
PARAMETER C_MEM_PARTNO = MT46V32M8-6T
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_USE_STATIC_PHY = 1
PARAMETER C_MEM_CLK_WIDTH = 3
PARAMETER C_STATIC_PHY_RDEN_DELAY = 6
PARAMETER C_PIM1_BASETYPE = 2
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_MPMC_HIGHADDR = 0x1fffffff
PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000
PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff
BUS_INTERFACE SPLB0 = ppc405_0_iplb1
BUS_INTERFACE SPLB1 = ppc405_0_dplb1
BUS_INTERFACE MPMC_CTRL = plb0
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
PORT MPMC_DCM_PSINCDEC = Static_Phy_DCM_PSINCDEC
PORT MPMC_DCM_PSEN = Static_Phy_DCM_PSEN
PORT MPMC_DCM_PSDONE = Static_Phy_DCM_PSDONE
PORT MPMC_Clk_Mem = dcm_DDR_CLK0
PORT MPMC_Clk0 = sys_clk_s
PORT MPMC_Clk90 = sys_clk_90_s
PORT MPMC_Rst = sys_periph_reset
END

BEGIN dcm_module
PARAMETER INSTANCE = dcm_DDR
PARAMETER HW_VER = 1.00.d
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_PHASE_SHIFT = 0
PARAMETER C_CLKOUT_PHASE_SHIFT = VARIABLE
# Note: Exact value may vary by device. #
# For example, Virtex-4 ES devices require VARIABLE_POSITIVE (AR#20529) #
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = sys_clk_s
# PORT CLK0 = MPMC_Clk_Mem
# PORT CLKFB = MPMC_Clk_Mem
PORT RST = Dcm_all_locked
PORT LOCKED = dcm_DDR_LOCKED_0
PORT PSCLK = sys_clk_s
PORT PSINCDEC = Static_Phy_DCM_PSINCDEC
PORT PSEN = Static_Phy_DCM_PSEN
PORT PSDONE = Static_Phy_DCM_PSDONE
PORT CLK0 = dcm_DDR_CLK0
PORT CLKFB = dcm_DDR_CLK0
END