do
  {
    i = 0;
    mask = 1;

    /*
     * Test each bit in turn looking for an active interrupt. Once one is
     * found, the interrupt handler asigned by a call to alt_irq_register() is
     * called to clear the interrupt condition.
     */

    do
    {
      if (active & mask)
      {
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
        alt_irq[i].handler(alt_irq[i].context);
#else
        alt_irq[i].handler(alt_irq[i].context, i);
#endif
        break;
      }
      mask <<= 1;
      i++;

    } while (1);

    active = alt_irq_pending ();
    
  } while (active);

void init()
{
    //настройка таймера для HEX монитора
    IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMERSEGLED_BASE, 0);
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
    alt_ic_isr_register(TIMERSEGLED_IRQ_INTERRUPT_CONTROLLER_ID, TIMERSEGLED_IRQ, timerHexInt, (void*)TIMERSEGLED_BASE, NULL);    // обозначение прерывания
        /* Start timer */
    IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMERSEGLED_BASE, ALTERA_AVALON_TIMER_CONTROL_ITO_MSK    | ALTERA_AVALON_TIMER_CONTROL_START_MSK);
#else
    /* Register the interrupt */
    alt_irq_register(TIMERSEGLED_IRQ, TIMERSEGLED_BASE, timerHexInt);
    /* Start timer */
    IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMERSEGLED_BASE, ALTERA_AVALON_TIMER_CONTROL_ITO_MSK
    | ALTERA_AVALON_TIMER_CONTROL_START_MSK);
#endif
}

/*
#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
* CPU configuration
*
*/

#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x1010820
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x0
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 25
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_DCACHE_SIZE 2048
#define ALT_CPU_EXCEPTION_ADDR 0x1008020
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 2048
#define ALT_CPU_INITDA_SUPPORTED
#define ALT_CPU_INST_ADDR_WIDTH 25
#define ALT_CPU_NAME "cpu_0"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_RESET_ADDR 0x1008000


/*
* CPU configuration (with legacy prefix - don't use these anymore)
*
*/

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x1010820
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x0
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 25
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_EXCEPTION_ADDR 0x1008020
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 2048
#define NIOS2_INITDA_SUPPORTED
#define NIOS2_INST_ADDR_WIDTH 25
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_RESET_ADDR 0x1008000


/*
* Custom instruction macros
*
*/

#define ALT_CI_CONVERTER(A) __builtin_custom_ini(ALT_CI_CONVERTER_N,(A))
#define ALT_CI_CONVERTER_N 0x0


/*
* Define for each module class mastered by the CPU
*
*/

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SPI
#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_UART
#define __ALTERA_NIOS2
#define __ALTERA_NIOS_CUSTOM_INSTR_ENDIAN_CONVERTER


/*
* GPIO configuration
*
*/

#define ALT_MODULE_CLASS_GPIO altera_avalon_pio
#define GPIO_BASE 0x1011180
#define GPIO_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPIO_CAPTURE 0
#define GPIO_DATA_WIDTH 8
#define GPIO_DO_TEST_BENCH_WIRING 0
#define GPIO_DRIVEN_SIM_VALUE 0x0
#define GPIO_EDGE_TYPE "NONE"
#define GPIO_FREQ 50000000u
#define GPIO_HAS_IN 0
#define GPIO_HAS_OUT 1
#define GPIO_HAS_TRI 0
#define GPIO_IRQ -1
#define GPIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define GPIO_IRQ_TYPE "NONE"
#define GPIO_NAME "/dev/GPIO"
#define GPIO_RESET_VALUE 0x0
#define GPIO_SPAN 16
#define GPIO_TYPE "altera_avalon_pio"


/*
* IOHex configuration
*
*/

#define ALT_MODULE_CLASS_IOHex altera_avalon_pio
#define IOHEX_BASE 0x10111a0
#define IOHEX_BIT_CLEARING_EDGE_REGISTER 0
#define IOHEX_BIT_MODIFYING_OUTPUT_REGISTER 0
#define IOHEX_CAPTURE 0
#define IOHEX_DATA_WIDTH 32
#define IOHEX_DO_TEST_BENCH_WIRING 0
#define IOHEX_DRIVEN_SIM_VALUE 0x0
#define IOHEX_EDGE_TYPE "NONE"
#define IOHEX_FREQ 50000000u
#define IOHEX_HAS_IN 0
#define IOHEX_HAS_OUT 1
#define IOHEX_HAS_TRI 0
#define IOHEX_IRQ -1
#define IOHEX_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IOHEX_IRQ_TYPE "NONE"
#define IOHEX_NAME "/dev/IOHex"
#define IOHEX_RESET_VALUE 0xffffffff
#define IOHEX_SPAN 16
#define IOHEX_TYPE "altera_avalon_pio"


/*
* IOLed configuration
*
*/

#define ALT_MODULE_CLASS_IOLed altera_avalon_pio
#define IOLED_BASE 0x1011190
#define IOLED_BIT_CLEARING_EDGE_REGISTER 0
#define IOLED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define IOLED_CAPTURE 0
#define IOLED_DATA_WIDTH 10
#define IOLED_DO_TEST_BENCH_WIRING 0
#define IOLED_DRIVEN_SIM_VALUE 0x0
#define IOLED_EDGE_TYPE "NONE"
#define IOLED_FREQ 50000000u
#define IOLED_HAS_IN 0
#define IOLED_HAS_OUT 1
#define IOLED_HAS_TRI 0
#define IOLED_IRQ -1
#define IOLED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define IOLED_IRQ_TYPE "NONE"
#define IOLED_NAME "/dev/IOLed"
#define IOLED_RESET_VALUE 0x0
#define IOLED_SPAN 16
#define IOLED_TYPE "altera_avalon_pio"


/*
* System configuration
*
*/

#define ALT_DEVICE_FAMILY "CYCLONEIII"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x10111b0
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/terminal"
#define ALT_STDIN_BASE 0x1011160
#define ALT_STDIN_DEV terminal
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_uart"
#define ALT_STDOUT "/dev/terminal"
#define ALT_STDOUT_BASE 0x1011160
#define ALT_STDOUT_DEV terminal
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_uart"
#define ALT_SYSTEM_NAME "cpuNiosII"


/*
* hal configuration
*
*/

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK TIMER_SYS


/*
* jtag_uart_0 configuration
*
*/

#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x10111b0
#define JTAG_UART_0_IRQ 0
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
#define JTAG_UART_0_READ_DEPTH 64
#define JTAG_UART_0_READ_THRESHOLD 8
#define JTAG_UART_0_SPAN 8
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_0_WRITE_DEPTH 64
#define JTAG_UART_0_WRITE_THRESHOLD 8


/*
* onchip_memory2_0 configuration
*
*/

#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_BASE 0x1008000
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "Automatic"
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "onchip_memory2_0"
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
#define ONCHIP_MEMORY2_0_IRQ -1
#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "Auto"
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 30720u
#define ONCHIP_MEMORY2_0_SPAN 30720
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY2_0_WRITABLE 1


/*
* sdram_0 configuration
*
*/

#define ALT_MODULE_CLASS_sdram_0 altera_avalon_new_sdram_controller
#define SDRAM_0_BASE 0x800000
#define SDRAM_0_CAS_LATENCY 3
#define SDRAM_0_CONTENTS_INFO ""
#define SDRAM_0_INIT_NOP_DELAY 0.0
#define SDRAM_0_INIT_REFRESH_COMMANDS 2
#define SDRAM_0_IRQ -1
#define SDRAM_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SDRAM_0_IS_INITIALIZED 1
#define SDRAM_0_NAME "/dev/sdram_0"
#define SDRAM_0_POWERUP_DELAY 100.0
#define SDRAM_0_REFRESH_PERIOD 15.625
#define SDRAM_0_REGISTER_DATA_IN 1
#define SDRAM_0_SDRAM_ADDR_WIDTH 22
#define SDRAM_0_SDRAM_BANK_WIDTH 2
#define SDRAM_0_SDRAM_COL_WIDTH 8
#define SDRAM_0_SDRAM_DATA_WIDTH 16
#define SDRAM_0_SDRAM_NUM_BANKS 4
#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_0_SDRAM_ROW_WIDTH 12
#define SDRAM_0_SHARED_DATA 0
#define SDRAM_0_SIM_MODEL_BASE 1
#define SDRAM_0_SPAN 8388608
#define SDRAM_0_STARVATION_INDICATOR 0
#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_0_T_AC 5.5
#define SDRAM_0_T_MRD 3
#define SDRAM_0_T_RCD 20.0
#define SDRAM_0_T_RFC 70.0
#define SDRAM_0_T_RP 20.0
#define SDRAM_0_T_WR 14.0


/*
* spi_AD4360_9 configuration
*
*/

#define ALT_MODULE_CLASS_spi_AD4360_9 altera_avalon_spi
#define SPI_AD4360_9_BASE 0x1011080
#define SPI_AD4360_9_CLOCKMULT 1
#define SPI_AD4360_9_CLOCKPHASE 0
#define SPI_AD4360_9_CLOCKPOLARITY 0
#define SPI_AD4360_9_CLOCKUNITS "Hz"
#define SPI_AD4360_9_DATABITS 24
#define SPI_AD4360_9_DATAWIDTH 32
#define SPI_AD4360_9_DELAYMULT "1.0E-9"
#define SPI_AD4360_9_DELAYUNITS "ns"
#define SPI_AD4360_9_EXTRADELAY 0
#define SPI_AD4360_9_INSERT_SYNC 0
#define SPI_AD4360_9_IRQ 3
#define SPI_AD4360_9_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_AD4360_9_ISMASTER 1
#define SPI_AD4360_9_LSBFIRST 0
#define SPI_AD4360_9_NAME "/dev/spi_AD4360_9"
#define SPI_AD4360_9_NUMSLAVES 1
#define SPI_AD4360_9_PREFIX "spi_"
#define SPI_AD4360_9_SPAN 32
#define SPI_AD4360_9_SYNC_REG_DEPTH 2
#define SPI_AD4360_9_TARGETCLOCK 128000u
#define SPI_AD4360_9_TARGETSSDELAY "0.0"
#define SPI_AD4360_9_TYPE "altera_avalon_spi"


/*
* spi_AD5623 configuration
*
*/

#define ALT_MODULE_CLASS_spi_AD5623 altera_avalon_spi
#define SPI_AD5623_BASE 0x10110e0
#define SPI_AD5623_CLOCKMULT 1
#define SPI_AD5623_CLOCKPHASE 0
#define SPI_AD5623_CLOCKPOLARITY 0
#define SPI_AD5623_CLOCKUNITS "Hz"
#define SPI_AD5623_DATABITS 24
#define SPI_AD5623_DATAWIDTH 32
#define SPI_AD5623_DELAYMULT "1.0E-9"
#define SPI_AD5623_DELAYUNITS "ns"
#define SPI_AD5623_EXTRADELAY 0
#define SPI_AD5623_INSERT_SYNC 0
#define SPI_AD5623_IRQ 6
#define SPI_AD5623_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_AD5623_ISMASTER 1
#define SPI_AD5623_LSBFIRST 0
#define SPI_AD5623_NAME "/dev/spi_AD5623"
#define SPI_AD5623_NUMSLAVES 3
#define SPI_AD5623_PREFIX "spi_"
#define SPI_AD5623_SPAN 32
#define SPI_AD5623_SYNC_REG_DEPTH 2
#define SPI_AD5623_TARGETCLOCK 128000u
#define SPI_AD5623_TARGETSSDELAY "0.0"
#define SPI_AD5623_TYPE "altera_avalon_spi"


/*
* spi_ADF4350 configuration
*
*/

#define ALT_MODULE_CLASS_spi_ADF4350 altera_avalon_spi
#define SPI_ADF4350_BASE 0x1011060
#define SPI_ADF4350_CLOCKMULT 1
#define SPI_ADF4350_CLOCKPHASE 0
#define SPI_ADF4350_CLOCKPOLARITY 0
#define SPI_ADF4350_CLOCKUNITS "Hz"
#define SPI_ADF4350_DATABITS 32
#define SPI_ADF4350_DATAWIDTH 32
#define SPI_ADF4350_DELAYMULT "1.0E-9"
#define SPI_ADF4350_DELAYUNITS "ns"
#define SPI_ADF4350_EXTRADELAY 0
#define SPI_ADF4350_INSERT_SYNC 0
#define SPI_ADF4350_IRQ 2
#define SPI_ADF4350_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_ADF4350_ISMASTER 1
#define SPI_ADF4350_LSBFIRST 0
#define SPI_ADF4350_NAME "/dev/spi_ADF4350"
#define SPI_ADF4350_NUMSLAVES 2
#define SPI_ADF4350_PREFIX "spi_"
#define SPI_ADF4350_SPAN 32
#define SPI_ADF4350_SYNC_REG_DEPTH 2
#define SPI_ADF4350_TARGETCLOCK 128000u
#define SPI_ADF4350_TARGETSSDELAY "0.0"
#define SPI_ADF4350_TYPE "altera_avalon_spi"


/*
* spi_DAT_31R5 configuration
*
*/

#define ALT_MODULE_CLASS_spi_DAT_31R5 altera_avalon_spi
#define SPI_DAT_31R5_BASE 0x1011100
#define SPI_DAT_31R5_CLOCKMULT 1
#define SPI_DAT_31R5_CLOCKPHASE 0
#define SPI_DAT_31R5_CLOCKPOLARITY 0
#define SPI_DAT_31R5_CLOCKUNITS "Hz"
#define SPI_DAT_31R5_DATABITS 8
#define SPI_DAT_31R5_DATAWIDTH 16
#define SPI_DAT_31R5_DELAYMULT "1.0E-9"
#define SPI_DAT_31R5_DELAYUNITS "ns"
#define SPI_DAT_31R5_EXTRADELAY 0
#define SPI_DAT_31R5_INSERT_SYNC 0
#define SPI_DAT_31R5_IRQ 7
#define SPI_DAT_31R5_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_DAT_31R5_ISMASTER 1
#define SPI_DAT_31R5_LSBFIRST 0
#define SPI_DAT_31R5_NAME "/dev/spi_DAT_31R5"
#define SPI_DAT_31R5_NUMSLAVES 4
#define SPI_DAT_31R5_PREFIX "spi_"
#define SPI_DAT_31R5_SPAN 32
#define SPI_DAT_31R5_SYNC_REG_DEPTH 2
#define SPI_DAT_31R5_TARGETCLOCK 128000u
#define SPI_DAT_31R5_TARGETSSDELAY "0.0"
#define SPI_DAT_31R5_TYPE "altera_avalon_spi"


/*
* spi_FM25CL64 configuration
*
*/

#define ALT_MODULE_CLASS_spi_FM25CL64 altera_avalon_spi
#define SPI_FM25CL64_BASE 0x10110a0
#define SPI_FM25CL64_CLOCKMULT 1
#define SPI_FM25CL64_CLOCKPHASE 0
#define SPI_FM25CL64_CLOCKPOLARITY 0
#define SPI_FM25CL64_CLOCKUNITS "Hz"
#define SPI_FM25CL64_DATABITS 8
#define SPI_FM25CL64_DATAWIDTH 16
#define SPI_FM25CL64_DELAYMULT "1.0E-9"
#define SPI_FM25CL64_DELAYUNITS "ns"
#define SPI_FM25CL64_EXTRADELAY 0
#define SPI_FM25CL64_INSERT_SYNC 0
#define SPI_FM25CL64_IRQ 4
#define SPI_FM25CL64_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_FM25CL64_ISMASTER 1
#define SPI_FM25CL64_LSBFIRST 0
#define SPI_FM25CL64_NAME "/dev/spi_FM25CL64"
#define SPI_FM25CL64_NUMSLAVES 3
#define SPI_FM25CL64_PREFIX "spi_"
#define SPI_FM25CL64_SPAN 32
#define SPI_FM25CL64_SYNC_REG_DEPTH 2
#define SPI_FM25CL64_TARGETCLOCK 128000u
#define SPI_FM25CL64_TARGETSSDELAY "0.0"
#define SPI_FM25CL64_TYPE "altera_avalon_spi"


/*
* spi_TMP_121 configuration
*
*/

#define ALT_MODULE_CLASS_spi_TMP_121 altera_avalon_spi
#define SPI_TMP_121_BASE 0x10110c0
#define SPI_TMP_121_CLOCKMULT 1
#define SPI_TMP_121_CLOCKPHASE 0
#define SPI_TMP_121_CLOCKPOLARITY 0
#define SPI_TMP_121_CLOCKUNITS "Hz"
#define SPI_TMP_121_DATABITS 16
#define SPI_TMP_121_DATAWIDTH 16
#define SPI_TMP_121_DELAYMULT "1.0E-9"
#define SPI_TMP_121_DELAYUNITS "ns"
#define SPI_TMP_121_EXTRADELAY 0
#define SPI_TMP_121_INSERT_SYNC 0
#define SPI_TMP_121_IRQ 5
#define SPI_TMP_121_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_TMP_121_ISMASTER 1
#define SPI_TMP_121_LSBFIRST 0
#define SPI_TMP_121_NAME "/dev/spi_TMP_121"
#define SPI_TMP_121_NUMSLAVES 2
#define SPI_TMP_121_PREFIX "spi_"
#define SPI_TMP_121_SPAN 32
#define SPI_TMP_121_SYNC_REG_DEPTH 2
#define SPI_TMP_121_TARGETCLOCK 128000u
#define SPI_TMP_121_TARGETSSDELAY "0.0"
#define SPI_TMP_121_TYPE "altera_avalon_spi"


/*
* sysid configuration
*
*/

#define ALT_MODULE_CLASS_sysid altera_avalon_sysid
#define SYSID_BASE 0x10111b8
#define SYSID_ID 680655224u
#define SYSID_IRQ -1
#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_NAME "/dev/sysid"
#define SYSID_SPAN 8
#define SYSID_TIMESTAMP 1295254251u
#define SYSID_TYPE "altera_avalon_sysid"


/*
* terminal configuration
*
*/

#define ALT_MODULE_CLASS_terminal altera_avalon_uart
#define TERMINAL_BASE 0x1011160
#define TERMINAL_BAUD 115200
#define TERMINAL_DATA_BITS 8
#define TERMINAL_FIXED_BAUD 1
#define TERMINAL_FREQ 50000000u
#define TERMINAL_IRQ 10
#define TERMINAL_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TERMINAL_NAME "/dev/terminal"
#define TERMINAL_PARITY 'N'
#define TERMINAL_SIM_CHAR_STREAM ""
#define TERMINAL_SIM_TRUE_BAUD 0
#define TERMINAL_SPAN 32
#define TERMINAL_STOP_BITS 1
#define TERMINAL_SYNC_REG_DEPTH 2
#define TERMINAL_TYPE "altera_avalon_uart"
#define TERMINAL_USE_CTS_RTS 0
#define TERMINAL_USE_EOP_REGISTER 0


/*
* timerSegLed configuration
*
*/

#define ALT_MODULE_CLASS_timerSegLed altera_avalon_timer
#define TIMERSEGLED_ALWAYS_RUN 0
#define TIMERSEGLED_BASE 0x1011140
#define TIMERSEGLED_COUNTER_SIZE 32
#define TIMERSEGLED_FIXED_PERIOD 0
#define TIMERSEGLED_FREQ 50000000u
#define TIMERSEGLED_IRQ 9
#define TIMERSEGLED_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMERSEGLED_LOAD_VALUE 4999999ULL
#define TIMERSEGLED_MULT 0.0010
#define TIMERSEGLED_NAME "/dev/timerSegLed"
#define TIMERSEGLED_PERIOD 100
#define TIMERSEGLED_PERIOD_UNITS "ms"
#define TIMERSEGLED_RESET_OUTPUT 0
#define TIMERSEGLED_SNAPSHOT 1
#define TIMERSEGLED_SPAN 32
#define TIMERSEGLED_TICKS_PER_SEC 10u
#define TIMERSEGLED_TIMEOUT_PULSE_OUTPUT 0
#define TIMERSEGLED_TYPE "altera_avalon_timer"


/*
* timer_0 configuration
*
*/

#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x1011120
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 50000000u
#define TIMER_0_IRQ 8
#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_0_LOAD_VALUE 499999ULL
#define TIMER_0_MULT 0.0010
#define TIMER_0_NAME "/dev/timer_0"
#define TIMER_0_PERIOD 10
#define TIMER_0_PERIOD_UNITS "ms"
#define TIMER_0_RESET_OUTPUT 0
#define TIMER_0_SNAPSHOT 1
#define TIMER_0_SPAN 32
#define TIMER_0_TICKS_PER_SEC 100u
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_0_TYPE "altera_avalon_timer"


/*
* timer_sys configuration
*
*/

#define ALT_MODULE_CLASS_timer_sys altera_avalon_timer
#define TIMER_SYS_ALWAYS_RUN 0
#define TIMER_SYS_BASE 0x1011000
#define TIMER_SYS_COUNTER_SIZE 64
#define TIMER_SYS_FIXED_PERIOD 1
#define TIMER_SYS_FREQ 50000000u
#define TIMER_SYS_IRQ 11
#define TIMER_SYS_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_SYS_LOAD_VALUE 49ULL
#define TIMER_SYS_MULT 1.0E-6
#define TIMER_SYS_NAME "/dev/timer_sys"
#define TIMER_SYS_PERIOD 1
#define TIMER_SYS_PERIOD_UNITS "us"
#define TIMER_SYS_RESET_OUTPUT 0
#define TIMER_SYS_SNAPSHOT 1
#define TIMER_SYS_SPAN 64
#define TIMER_SYS_TICKS_PER_SEC 1000000u
#define TIMER_SYS_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_SYS_TYPE "altera_avalon_timer"


/*
* uart_0 configuration
*
*/

#define ALT_MODULE_CLASS_uart_0 altera_avalon_uart
#define UART_0_BASE 0x1011040
#define UART_0_BAUD 115200
#define UART_0_DATA_BITS 8
#define UART_0_FIXED_BAUD 1
#define UART_0_FREQ 50000000u
#define UART_0_IRQ 1
#define UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define UART_0_NAME "/dev/uart_0"
#define UART_0_PARITY 'N'
#define UART_0_SIM_CHAR_STREAM ""
#define UART_0_SIM_TRUE_BAUD 0
#define UART_0_SPAN 32
#define UART_0_STOP_BITS 1
#define UART_0_SYNC_REG_DEPTH 2
#define UART_0_TYPE "altera_avalon_uart"
#define UART_0_USE_CTS_RTS 0
#define UART_0_USE_EOP_REGISTER 0

#endif /* __SYSTEM_H_ */