Вот пробую, но не получается ....
Внешний клок подал на копыто GCLK0 ...
Пропустил через IBUFG ...
Сгенерил корегенератором DCM без доп. входов и выходов (только CLKIN и CLK0)...
Получилось :
Attributes for DCM_SP, blkname = DCM_SP_INST
CLK_FEEDBACK = 1X
CLKDV_DIVIDE = 2
CLKFX_DIVIDE = 1
CLKFX_MULTIPLY = 4
CLKIN_DIVIDE_BY_2 = FALSE
CLKIN_PERIOD = 20.000
CLKOUT_PHASE_SHIFT = NONE
DESKEW_ADJUST = SYSTEM_SYNCHRONOUS
DFS_FREQUENCY_MODE = LOW
DLL_FREQUENCY_MODE = LOW
DUTY_CYCLE_CORRECTION = TRUE
FACTORY_JF = 16'hC080
PHASE_SHIFT = 0
STARTUP_WAIT = FALSE
Каким образом влепить DCM в проект?
Во View HDL Source вижу (правда на Verilog ):
////////////////////////////////////////////////////////////////////////////////
// Copyright © 1995-2008 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 10.1
// \ \ Application : xaw2verilog
// / / Filename : DCM_CLOCK.v
// /___/ /\ Timestamp : 05/03/2011 11:52:15
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle D:/XILINX_PROJECTS_2010/EVK_DCM/1/DCM_CLOCK.xaw -st DCM_CLOCK.v
//Design Name: DCM_CLOCK
//Device: xc3s50an-5tqg144
//
// Module DCM_CLOCK
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module DCM_CLOCK(CLKIN_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT);
input CLKIN_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
defparam DCM_SP_INST.CLKFX_DIVIDE = 1;
defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
defparam DCM_SP_INST.PHASE_SHIFT = 0;
defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
endmodule
Счас попробую ....