Настройка модуля управления ЖК-индикатором на примере микроконтроллера NXP LPC2478 и TFT-матирицы MTF-TQ57SN721-AV
CODE
void InitPanel(void)
{
unsigned long i;
PCONP |= 1<<20; // bit 20 - PCLCD - LCD controller power control bit.
PINSEL11 = ( (5<<1) | 1); // This register is used to select the LCD function and the LCD mode on the LPC247x:
// TFT 16-bit (5:6:5 mode), LCD port enable
PINSEL4 &= ~(3<<4); // P2[2] LCDDCLK
PINSEL4 &= ~(3<<6); // P2[3] LCDFP
PINSEL4 &= ~(3<<8); // P2[4] LCDENAB/LCDM
PINSEL4 &= ~(3<<10); // P2[5] LCDLP
PINSEL4 |= ((3<<4) | (3<<6) | (3<<8) | (3<<10)); // 1111 1111 0000
// LCDVD
// страницы 176,178,281 UM LPC2400
PINSEL3 &= ~(3<<8); // P1[20] LCDVD[6]/LCDVD[10] G0 LCDVD[10]
PINSEL3 &= ~(3<<10); // P1[21] LCDVD[7]/LCDVD[11] G1 LCDVD[11]
PINSEL3 &= ~(3<<12); // P1[22] LCDVD[8]/LCDVD[12] G2 LCDVD[12]
PINSEL3 &= ~(3<<14); // P1[23] LCDVD[9]/LCDVD[13] G3 LCDVD[13]
PINSEL3 &= ~(3<<16); // P1[24] LCDVD[10]/LCDVD[14] G4 LCDVD[14]
PINSEL3 &= ~(3<<18); // P1[25] LCDVD[11]/LCDVD[15] G5 LCDVD[15]
PINSEL3 &= ~(3<<20); // P1[26] LCDVD[12]/LCDVD[20] B1 LCDVD[20]
PINSEL3 &= ~(3<<22); // P1[27] LCDVD[13]/LCDVD[21] B2 LCDVD[21]
PINSEL3 &= ~(3<<24); // P1[28] LCDVD[14]/LCDVD[22] B3 LCDVD[22]
PINSEL3 &= ~(3<<26); // P1[29] LCDVD[15]/LCDVD[23] B4 LCDVD[23]
PINSEL3 |= ( (1<<8) | (1<<10) | (1<<12) | (1<<14) | (1<<16) | (1<<18) | (1<<20) | (1<<22) | (1<<24) | (1<<26) );
// 0101 0101 0101 0101 0101 0000 0000
PINSEL4 &= ~(3<<12); // P2[6] LCDVD[0]/LCDVD[4] R1 LCDVD[4]
PINSEL4 &= ~(3<<14); // P2[7] LCDVD[1]/LCDVD[5] R2 LCDVD[5]
PINSEL4 &= ~(3<<16); // P2[8] LCDVD[2]/LCDVD[6] R3 LCDVD[6]
PINSEL4 &= ~(3<<18); // P2[9] LCDVD[3]/LCDVD[7] R4 LCDVD[7]
PINSEL4 &= ~(3<<24); // P2[12] LCDVD[4]/LCDVD[3]/LCDVD[8]/LCDVD[18] R0 LCDVD[3]
PINSEL4 &= ~(3<<26); // P2[13] LCDVD[5]/LCDVD[9]/LCDVD[19] B0 LCDVD[19]
PINSEL4 |= ( (3<<12) | (3<<14) | (3<<16) | (3<<18) | (1<<24) | (1<<26) );
// 0101 0101 0000 1111 1111 1111 1111 0000
LCD_CFG_REG = 2; // LCD panel clock prescaler selection.
// The value in the this register plus 1 is used to divide the selected
// input clock (see the CLKSEL bit in the LCD_POL register), to
// produce the panel clock.
// MTF-TQ57SN721-AV:
// DCLK period TOSC = 156 ns
// Frequency FOSC = 6.4 MHz
LCD_TIMH_REG = ( (1<<24) | (1<<16) | (50<<8) | (((320/16)-1)<<2));
// bit 31:24 - HBP - Horizontal back porch.
// The 8-bit HBP field is used to specify the number of pixel clock
// periods inserted at the beginning of each line or row of pixels.
// After the line clock for the previous line has been deasserted, the
// value in HBP counts the number of pixel clocks to wait before
// starting the next display line. HBP can generate a delay of 1-256
// pixel clock cycles. Program with desired value minus 1.
// bit 23:16 - HFP - Horizontal front porch.
// The 8-bit HFP field sets the number of pixel clock intervals at the
// end of each line or row of pixels, before the LCD line clock is
// pulsed. When a complete line of pixels is transmitted to the LCD
// driver, the value in HFP counts the number of pixel clocks to wait
// before asserting the line clock. HFP can generate a period of
// 1-256 pixel clock cycles. Program with desired value minus 1.
// bit 15:8 - HSW - Horizontal synchronization pulse width.
// The 8-bit HSW field specifies the pulse width of the line clock in
// passive mode, or the horizontal synchronization pulse in active
// mode. Program with desired value minus 1.
// bit 7:2 - PPL - Pixels-per-line.
// The PPL bit field specifies the number of pixels in each line or
// row of the screen. PPL is a 6-bit value that represents between
// 16 and 1024 pixels per line. PPL counts the number of pixel
// clocks that occur before the HFP is applied.
// Program the value required divided by 16, minus 1. Actual
// pixels-per-line = 16 * (PPL + 1). For example, to obtain 320
// pixels per line, program PPL as (320/16) -1 = 19.
LCD_TIMV_REG = ( (1<<24) | (1<<16) | (1<<10) | (240) );
// bit 31:24 - VBP - Vertical back porch("подход").
// This is the number of inactive lines at the start of a frame, after
// the vertical synchronization period. The 8-bit VBP field specifies
// the number of line clocks inserted at the beginning of each
// frame. The VBP count starts immediately after the vertical
// synchronization signal for the previous frame has been negated
// for active mode, or the extra line clocks have been inserted as
// specified by the VSW bit field in passive mode. After this has
// occurred, the count value in VBP sets the number of line clock
// periods inserted before the next frame. VBP generates 0–255
// extra line clock cycles. Program to zero on passive displays for
// improved contrast.
// bit 23:16 - VFP - Vertical front porch.
// This is the number of inactive lines at the end of a frame, before
// the vertical synchronization period. The 8-bit VFP field specifies
// the number of line clocks to insert at the end of each frame.
// When a complete frame of pixels is transmitted to the LCD
// display, the value in VFP is used to count the number of line
// clock periods to wait.
// After the count has elapsed, the vertical synchronization signal,
// LCDFP, is asserted in active mode, or extra line clocks are
// inserted as specified by the VSW bit-field in passive mode. VFP
// generates 0–255 line clock cycles. Program to zero on passive
// displays for improved contrast.
// bit 15:10 - VSW - Vertical synchronization pulse width.
// This is the number of horizontal synchronization lines. The 6-bit
// VSW field specifies the pulse width of the vertical
// synchronization pulse. Program the register with the number of
// lines required, minus one.
// The number of horizontal synchronization lines must be small
// (for example, program to zero) for passive STN LCDs. The
// higher the value the worse the contrast on STN LCDs.
// bit 9:0 - LPP - Lines per panel.
// This is the number of active lines per screen. The LPP field
// specifies the total number of lines or rows on the LCD panel
// being controlled. LPP is a 10-bit value allowing between 1 and
// 1024 lines. Program the register with the number of lines per
// LCD panel, minus 1. For dual panel displays, program the
// register with the number of lines on each of the upper and lower
// panels.
LCD_POL_REG = ( (0<<26) | (((320/1)-1)<<16) | (1<<13/* IPC */) | (1<<12) | (0<<5));
// bit 31:27 - PCD_HI - Upper five bits of panel clock divisor.
// See description for PCD_LO, in bits [4:0] of this register.
// bit 26 - BCD - Bypass pixel clock divider.
// Setting this to 1 bypasses the pixel clock divider logic. This is
// mainly used for TFT displays.
// bit 25:16 - CPL - Clocks per line.
// This field specifies the number of actual LCDDCLK clocks to the
// LCD panel on each line. This is the number of PPL divided by
// either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for
// color passive), minus one. This must be correctly programmed in
// addition to the PPL bit in the LCD_TIMH register for the LCD
// display to work correctly.
// bit 15 - reserved - Reserved, user software should not write ones to reserved bits.
// The value read from a reserved bit is not defined.
// bit 14 - IOE - Invert output enable.
// This bit selects the active polarity of the output enable signal in
// that indicates to the LCD panel when valid display data is
// available. In active display mode, data is driven onto the LCD
// data lines at the programmed edge of LCDDCLK when
// LCDENAB is in its active state.
// 0 = LCDENAB output pin is active HIGH in TFT mode.
// 1 = LCDENAB output pin is active LOW in TFT mode.
// bit 13 - IPC - Invert panel clock.
// The IPC bit selects the edge of the panel clock on which pixel
// data is driven out onto the LCD data lines.
// 0 = Data is driven on the LCD data lines on the rising edge of
// LCDDCLK.
// 1 = Data is driven on the LCD data lines on the falling edge of
// LCDDCLK.
// bit 12 - IHS - Invert horizontal synchronization.
// The IHS bit inverts the polarity of the LCDLP signal.
// 0 = LCDLP pin is active HIGH and inactive LOW.
// 1 = LCDLP pin is active LOW and inactive HIGH.
// bit 11 - IVS - Invert vertical synchronization.
// The IVS bit inverts the polarity of the LCDFP signal.
// 0 = LCDFP pin is active HIGH and inactive LOW.
// 1 = LCDFP pin is active LOW and inactive HIGH.
// bit 10:6 - ACB - AC bias pin frequency.
// The AC bias pin frequency is only applicable to STN displays.
// These require the pixel voltage polarity to periodically reverse to
// prevent damage caused by DC charge accumulation. Program
// this field with the required value minus one to apply the number
// of line clocks between each toggle of the AC bias pin,
// LCDENAB. This field has no effect if the LCD is operating in TFT
// mode, when the LCDENAB pin is used as a data enable signal.
// bit 5 - CLKSEL - Clock Select.
// This bit controls the selection of the source for LCDCLK.
// 0 = the clock source for the LCD block is HCLK.
// 1 = the clock source for the LCD block is LCDDCLK.
// bit 4:0 - PCD_LO - Lower five bits of panel clock divisor.
// The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this
// register) and PCD_LO, is used to derive the LCD panel clock
// frequency LCDDCLK from the input clock, LCDDCLK =
// LCDCLK/(PCD+2).
// For monochrome STN displays with a 4 or 8-bit interface, the
// panel clock is a factor of four and eight down from the actual
// individual pixel clock rate. For color STN displays, 22/3 pixels
// are output per LCDDCLK cycle, so the panel clock is 0.375 times
// the pixel rate.
// For TFT displays, the pixel clock divider can be bypassed by
// setting the BCD bit in this register.
// Note: data path latency forces some restrictions on the usable
// minimum values for the panel clock divider in STN modes:
// Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3).
// Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6).
// Single panel monochrome 4-bit interface mode, PCD =
// 2(LCDDCLK = LCDCLK/4).
// Dual panel monochrome 4-bit interface mode and single panel
// monochrome 8-bit interface mode, PCD = 6(LCDDCLK =
// LCDCLK/8).
// Dual panel monochrome 8-bit interface mode, PCD =
// 14(LCDDCLK = LCDCLK/16).
LCD_CTRL_REG = ((1<<5) | (6<<1) | (1<<8));
// bit 31:17 - reserved - Reserved, user software should not write ones to reserved bits.
// The value read from a reserved bit is not defined.
// bit 16 - WATERMARK - LCD DMA FIFO watermark level.
// Controls when DMA requests are generated:
// 0 = An LCD DMA request is generated when either of the DMA
// FIFOs have four or more empty locations.
// 1 = An LCD DMA request is generated when either of the DMA
// FIFOs have eight or more empty locations.
// bit 15:14 - reserved - Reserved, user software should not write ones to reserved bits.
// The value read from a reserved bit is not defined.
// bit 13:12 - LcdVComp - LCD Vertical Compare Interrupt.
// Generate VComp interrupt at:
// 00 = start of vertical synchronization.
// 01 = start of back porch.
// 10 = start of active video.
// 11 = start of front porch.
// bit 11 - LcdPwr - LCD power enable.
// 0 = power not gated through to LCD panel and LCDV[23:0]
// signals disabled, (held LOW).
// 1 = power gated through to LCD panel and LCDV[23:0] signals
// enabled, (active).
// See LCD power up and power down sequence for details on
// LCD power sequencing.
// bit 10 - BEPO - Big-Endian Pixel Ordering.
// 1 = big-endian pixel ordering within a byte.
// Controls pixel ordering within a byte:
// 0 = little-endian ordering within a byte.
// The BEPO bit selects between little and big-endian pixel packing
// for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp
// pixel formats.
// See Pixel serializer for more information on the data format.
// bit 9 - BEBO - Big-endian Byte Order.
// Controls byte ordering in memory:
// 0 = little-endian byte order.
// 1 = big-endian byte order.
// bit 8 - BGR - Color format selection.
// 0 = RGB: normal output.
// 1 = BGR: red and blue swapped.
// bit 7 - LcdDual - Single or Dual LCD panel selection.
// STN LCD interface is:
// 0 = single-panel.
// 1 = dual-panel.
// bit 6 - LcdMono8 - Monochrome LCD interface width.
// This bit controls whether a monochrome STN LCD uses a 4 or
// 8-bit parallel interface. It has no meaning in other modes and
// must be programmed to zero.
// 0 = monochrome LCD uses a 4-bit interface.
// 1 = monochrome LCD uses a 8-bit interface.
// bit 5 - LcdTFT - LCD panel TFT type selection.
// 0 = LCD is an STN display. Use gray scaler.
// 1 = LCD is a TFT display. Do not use gray scaler.
// bit 4 - LcdBW - STN LCD monochrome/color selection.
// 0 = STN LCD is color.
// 1 = STN LCD is monochrome.
// This bit has no meaning in TFT mode.
// bit 3:1 - LcdBpp - LCD bits per pixel:
// Selects the number of bits per LCD pixel:
// 000 = 1 bpp.
// 001 = 2 bpp.
// 010 = 4 bpp.
// 011 = 8 bpp.
// 100 = 16 bpp.
// 101 = 24 bpp (TFT panel only).
// 110 = 16 bpp, 5:6:5 mode.
// 111 = 12 bpp, 4:4:4 mode.
// bit 0 - LcdEn - LCD enable control bit.
// 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP,
// LCDENAB, and LCDLE are low.
// 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP,
// LCDENAB, and LCDLE are high.
// See LCD power up and power down sequence for details on
// LCD power sequencing.
// --------------------------
// LCD is a TFT display.
// 16 bpp, 5:6:5 mode.
// BGR: red and blue swapped.
// указатель на пространство в ОЗУ для хранения байтовой копии экрана (пиксель = 2 байта)
LCD_UPBASE_REG = BUFFER_ADDR;
LCD_LPBASE_REG = BUFFER_ADDR;
for(i=0;i<50000;i++); // небольшая пауза
LCD_CTRL_REG |= 1; // LCD enabled. Signals LCDLP, LCDDCLK, LCDFP,LCDENAB, and LCDLE are high.
for(i=0;i<50000;i++); // небольшая пауза
LCD_CTRL_REG |= 1<<11; // power gated through to LCD panel and LCDV[23:0] signals enabled, (active).
}
