/*Конфигурация таймера TIM1*/

TIM1->PSC = 0x0; // установка делителя счетчика
TIM1->ARR = 0xFFFF; //установка макс. значения регистра счетчика

TIM1->CCMR1 &= ~TIM_CCMR1_CC1S; // отчищаем флаги
TIM1->CCMR1 |= TIM_CCMR1_CC1S_0; //
TIM1->CCMR1 &= ~TIM_CCMR1_IC1F;
TIM1->CCMR1 |= (TIM_CCMR1_IC1F_2|TIM_CCMR1_IC1F_3);
TIM1->CCER |= TIM_CCER_CC1P;
TIM1->CCER &= ~TIM_CCMR1_IC1PSC;
TIM1->CCER |= TIM_CCER_CC1E;
TIM1->DIER |= TIM_DIER_CC1IE|TIM_DIER_UIE;
//канал 2
TIM1->CCR2 = 0xFFE; //записываем значение в регистр сравнения
TIM1->CCMR1|=(TIM_CCMR1_OC2M_0|TIM_CCMR1_OC2M_1); // устанавливаем выход таймера в режим переключателя
TIM1->CCER|= TIM_CCER_CC2E;
TIM1->DIER |= TIM_DIER_CC2IE;

//канал 3
TIM1->CCMR2 &= ~TIM_CCMR2_CC3S; // отчищаем флаги
TIM1->CCMR2 |= TIM_CCMR2_CC3S_0; //
TIM1->CCMR2 &= ~TIM_CCMR2_IC3F;
TIM1->CCMR2 |= (TIM_CCMR2_IC3F_2|TIM_CCMR2_IC3F_3);
TIM1->CCER |= TIM_CCER_CC3P;
TIM1->CCER &= ~TIM_CCMR2_IC3PSC;
TIM1->CCER |= TIM_CCER_CC3E;
TIM1->DIER |= TIM_DIER_CC3IE|TIM_DIER_UIE;


TIM1->CR1 |= TIM_CR1_CEN | TIM_CR1_ARPE; // включаем счетчик, разрешаем авто-перезагрузку

void TIM1_CC_IRQHandler(void)
{
if(TIM1->SR&TIM_SR_CC1IF)
{
TIM1->SR &=~TIM_SR_CC1IF;
cc1++;
}
if(TIM1->SR&TIM_SR_CC2IF)
{
TIM1->SR &=~TIM_SR_CC2IF;
cc2++;
}
if(TIM1->SR&TIM_SR_CC3IF)
{
TIM1->SR &=~TIM_SR_CC3IF;
cc3++;
}
}

  unsigned int status=AT91C_BASE_US1->US_CSR;
  status&=AT91C_BASE_US1->US_IMR;

TIM1->PSC = 7200-1; // установка делителя счетчика
TIM1->ARR = 0xFFF; //установка макс. значения регистра счетчика
TIM1->CR1 |= TIM_CR1_CEN | TIM_CR1_ARPE; // включаем счетчик, разрешаем авто-перезагрузку
TIM1->CCR1 = 0xFFE; //записываем значение в регистр сравнения
TIM1->CCMR1|=(TIM_CCMR1_OC1M_0|TIM_CCMR1_OC1M_1); // устанавливаем выход таймера в режим переключателя
TIM1->CCER|= TIM_CCER_CC1E;

Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
This bit selects whether IC1 or IC1 is used for trigger or capture operations.
0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1
is non-inverted.
1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is
inverted.
Note:This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 0 CC1E: Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled